ATtiny261-ESSZ datasheet(162/227 Pages) ATMEL

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7753C–AVR–07/09

ATtiny261/ATtiny461/ATtiny861

19.10.4

ADCSRB – ADC Control and Status Register B

• Bit 7– BIN: Bipolar Input Mode

The gain stage is working in the unipolar mode as default, but the bipolar mode can be selected

by writing the BIN bit in the ADCSRB register. In the unipolar mode only one-sided conversions

are supported and the voltage on the positive input must always be larger than the voltage on

the negative input. Otherwise the result is saturated to the voltage reference. In the bipolar mode

two-sided conversions are supported and the result is represented in the two’s complement

form. In the unipolar mode the resolution is 10 bits and the bipolar mode the resolution is 9 bits +

1 sign bit.

• Bits 6 – GSEL: Gain Select

The Gain Select bit selects the 32x gain instead of the 20x gain and the 8x gain instead of the 1x

gain when the Gain Select bit is written to one.

• Bits 5 – Res: Reserved Bit

This bit is a reserved bit in the ATtiny261/461/861 and will always read as zero.

• Bits 4 – REFS2: Reference Selection Bit

These bit selects either the voltage reference of 1.1 V or 2.56 V for the ADC, as shown in Table

19-4. If active channels are used, using AVCC or an external AREF higher than (AVCC - 1V) is

not recommended, as this will affect ADC accuracy. The internal voltage reference options may

not be used if an external voltage is being applied to the AREF pin.

• Bits 3 – MUX5: Analog Channel and Gain Selection Bit 5

The MUX5 bit is the MSB of the Analog Channel and Gain Selection bits. Refer to Table 19-5 for

details. If this bit is changed during a conversion, the change will not go into effect until this

conversion is complete (ADIF in ADCSRA is set).

• Bits 2:0 – ADTS2:0: ADC Auto Trigger Source

If ADATE in ADCSRA is written to one, the value of these bits selects which source will trigger

an ADC conversion. If ADATE is cleared, the ADTS2:0 settings will have no effect. A conversion

will be triggered by the rising edge of the selected Interrupt Flag. Note that switching from a trig-

ger source that is cleared to a trigger source that is set, will generate a positive edge on the

trigger signal. If ADEN in ADCSRA is set, this will start a conversion. Switching to Free Running

mode (ADTS[2:0]=0) will not cause a trigger event, even if the ADC Interrupt Flag is set.

Bit

0x03 (0x23)

BIN

GSEL

REFS2

MUX5

ADTS2

ADTS1

ADTS0

ADCSRB

Read/Write

R/W

Initial Value

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