ATtiny261-ESSZ datasheet(168/227 Pages) ATMEL

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168

7753C–AVR–07/09

ATtiny261/ATtiny461/ATtiny861

21.4.1

EEPROM Write Prevents Writing to SPMCSR

Note that an EEPROM write operation will block all software programming to Flash. Reading the

Fuses and Lock bits from software will also be prevented during the EEPROM write operation. It

is recommended that the user checks the status bit (EEPE) in the EECR Register and verifies

that the bit is cleared before writing to the SPMCSR Register.

21.4.2

Reading the Fuse and Lock Bits from Software

It is possible to read both the Fuse and Lock bits from software. To read the Lock bits, load the

Z-pointer with 0x0001 and set the RFLB and SPMEN bits in SPMCSR. When an LPM instruction

is executed within three CPU cycles after the RFLB and SPMEN bits are set in SPMCSR, the

value of the Lock bits will be loaded in the destination register. The RFLB and SPMEN bits will

auto-clear upon completion of reading the Lock bits or if no LPM instruction is executed within

three CPU cycles or no SPM instruction is executed within four CPU cycles. When RFLB and

SPMEN are cleared, LPM will work as described in the Instruction set Manual.

The algorithm for reading the Fuse Low byte is similar to the one described above for reading

the Lock bits. To read the Fuse Low byte, load the Z-pointer with 0x0000 and set the RFLB and

SPMEN bits in SPMCSR. When an LPM instruction is executed within three cycles after the

RFLB and SPMEN bits are set in the SPMCSR, the value of the Fuse Low byte (FLB) will be

loaded in the destination register as shown below. Refer to Table 22-5 on page 173 for a

detailed description and mapping of the Fuse Low byte.

Similarly, when reading the Fuse High byte, load 0x0003 in the Z-pointer. When an LPM instruc-

tion is executed within three cycles after the RFLB and SPMEN bits are set in the SPMCSR, the

value of the Fuse High byte (FHB) will be loaded in the destination register as shown below.

Refer to Table XXX on page XXX for detailed description and mapping of the Fuse High byte.

Fuse and Lock bits that are programmed, will be read as zero. Fuse and Lock bits that are

unprogrammed, will be read as one.

21.4.3

Preventing Flash Corruption

During periods of low V

CC, the Flash program can be corrupted because the supply voltage is

too low for the CPU and the Flash to operate properly. These issues are the same as for board

level systems using the Flash, and the same design solutions should be applied.

A Flash program corruption can be caused by two situations when the voltage is too low. First, a

regular write sequence to the Flash requires a minimum voltage to operate correctly. Secondly,

the CPU itself can execute instructions incorrectly, if the supply voltage for executing instructions

is too low.

Bit

––

LB2

LB1

Bit

7654

3210

FLB7

FLB6

FLB5

FLB4

FLB3

FLB2

FLB1

FLB0

Bit

7654

FHB7

FHB6

FHB5

FHB4

FHB3

FHB2

FHB1

FHB0

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