ATtiny261-ESSZ datasheet(169/227 Pages) ATMEL

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169

7753C–AVR–07/09

ATtiny261/ATtiny461/ATtiny861

Flash corruption can easily be avoided by following these design recommendations (one is

sufficient):

Keep the AVR RESET active (low) during periods of insufficient power supply voltage.

This can be done by enabling the internal Brown-out Detector (BOD) if the operating volt-

age matches the detection level. If not, an external low V

CC reset protection circuit can be

used. If a reset occurs while a write operation is in progress, the write operation will be

completed provided that the power supply voltage is sufficient.

Keep the AVR core in Power-down sleep mode during periods of low V

CC. This will pre-

vent the CPU from attempting to decode and execute instructions, effectively protecting

the SPMCSR Register and thus the Flash from unintentional writes.

21.4.4

Programming Time for Flash when Using SPM

The calibrated RC Oscillator is used to time Flash accesses. Table 21-1 shows the typical pro-

gramming time for Flash accesses from the CPU.

Note:

1. Minimum and maximum programming time is per individual operation.

21.5

21.5.1

SPMCSR – Store Program Memory Control and Status Register

The Store Program Memory Control and Status Register contains the control bits needed to con-

trol the Program memory operations.

• Bits 7:6 – Res: Reserved Bits

These bits are reserved bits in the ATtiny261/461/861 and always read as zero.

• Bit 5 – SIGRD: Signature Row Read

If this bit is written to one at the same time as SPMEN, the next LPM instruction within three

clock cycles will read a byte from the signature row into the destination register for details. An

SPM instruction within four cycles after SIGRD and SPMEN are set will have no effect.

• Bit 4 – CTPB: Clear Temporary Page Buffer

If the CTPB bit is written while filling the temporary page buffer, the temporary page buffer will be

cleared and the data will be lost.

• Bit 3 – RFLB: Read Fuse and Lock Bits

An LPM instruction within three cycles after RFLB and SPMEN are set in the SPMCSR Register,

will read either the Lock bits or the Fuse bits (depending on Z0 in the Z-pointer) into the destina-

tion register. See “EEPROM Write Prevents Writing to SPMCSR” on page 168 for details.

Table 21-1.

SPM Programming Time

(1)

Symbol

Min Programming Time

Max Programming Time

Flash write (Page Erase, Page Write, and

write Lock bits by SPM)

3.7 ms

4.5 ms

Bit

0x37 (0x57)

––

SIGRD

CTPB

RFLB

PGWRT

PGERS

SPMEN

SPMCSR

Read/Write

R/W

Initial Value

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