CDPCLK4 datasheet(154/274 Pages) ALTERA

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8–12

Chapter 8: External Memory Interfaces in the Cyclone III Device Family

Cyclone III Device Family Memory Interfaces Features

Cyclone III Device Handbook

July 2012

Altera Corporation

Volume 1

DDR Output Registers

A dedicated write DDIO block is implemented in the DDR output and output enable

paths. Figure 8–5 shows how Cyclone III device family dedicated write DDIO block is

implemented in the I/O element (IOE) registers.

The two DDR output registers are located in the I/O element (IOE) block. Two serial

data streams routed through datain_l and datain_h, are fed into two registers,

output register Ao

and output register Bo, respectively, on the same clock edge.

The output from output register Ao is captured on the falling edge of the clock, while

the output from output register Bo is captured on the rising edge of the clock. The

registered outputs are multiplexed by the common clock to drive the DDR output pin

at twice the data rate.

The DDR output enable path has a similar structure to the DDR output path in the

IOE block. The second output enable register provides the write preamble for the DQS

strobe in DDR external memory interfaces. This active-low output enable register

extends the high-impedance state of the pin by half a clock cycle to provide the

external memory’s DQS write preamble time specification.

Figure 8–5. Cyclone III Device Family Dedicated Write DDIO

IOE

Output Enable

-90° Shifted Clock

datain_l

Output Enable

data1

data0

IOE

Output Register A

data0

data1

datain_h

IOE

Output Register B

DDR Output Registers

DDR Output Enable Registers

DQ or DQS

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