CDPCLK4 datasheet(155/274 Pages) ALTERA

155 / 274 page

Chapter 8: External Memory Interfaces in the Cyclone III Device Family

8–13

Cyclone III Device Family Memory Interfaces Features

July 2012

Altera Corporation

Cyclone III Device Handbook

Volume 1

f For more information about Cyclone III device family IOE registers, refer to the

I/O Features in the Cyclone III Device Family chapter.

Figure 8–6 shows how the second output enable register extends the DQS

high-impedance state by half a clock cycle during a write operation.

OCT

Cyclone III device family supports calibrated on-chip series termination (RS OCT) in

both vertical and horizontal I/O banks. To use the calibrated OCT, you must use the

RUP and RDN pins for each RS OCT control block (one for each side). You can use

each OCT calibration block to calibrate one type of termination with the same VCCIO

for that given side.

f For more information about Cyclone III device family OCT calibration block, refer to

the Cyclone III Device I/O Features chapter.

PLL

When interfacing with external memory, the PLL is used to generate the memory

system clock, the write clock, the capture clock and the logic-core clock. The system

clock generates the DQS write signals, commands, and addresses. The write-clock is

shifted by -90° from the system clock and generates the DQ signals during writes. You

can use the PLL reconfiguration feature to calibrate the read-capture phase shift to

balance the setup and hold margins.

Figure 8–6. Extending the OE Disable by Half a Clock Cycle for a Write Transaction (1)

Note to Figure 8–6:

(1) The waveform reflects the software simulation result. The OE signal is an active low on the device. However, the Quartus II software implements

the signal as an active high and automatically adds an inverter before the AOE register D input.

System clock

(outclock for DQS)

OE for DQS

(from logic array)

DQS

Write Clock

(outclock for DQ,

-90 phase shifted

from System Clock)

datain_h

(from logic array)

datain_I

(from logic array)

OE for DQ

(from logic array)

Preamble

Postamble

Delay

by Half

a Clock

Cycle

90o

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