CDPCLK4 datasheet(187/274 Pages) ALTERA

187 / 274 page

Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family

9–29

Configuration Features

August 2012

Altera Corporation

Cyclone III Device Handbook

Volume 1

Word-Wide Multi-Device AP Configuration

The more efficient setup is one in which some of the slave devices are connected to the

LSB of DATA[7..0]and the remaining slave devices are connected to the MSB of

DATA[15..8]

. In the word-wide multi-device AP configuration, the nCEO pin of the

master device enables two separate daisy-chains of slave devices, allowing both

chains to be programmed concurrently, as shown in Figure 9–10.

1 In a multi-device AP configuration, the board trace length between the parallel flash

and the master device must follow the recommendations listed in Table 9–12.

Figure 9–10. Word-Wide Multi-Device AP Configuration

Notes to Figure 9–10:

(1) Connect the pull-up resistors to the VCCIO supply of the bank in which the pin resides.

(2) Connect the pull-up resistor to the VCCIO supply voltage of the I/O bank in which the nCE pin resides.

(3) The nCEO pin is left unconnected or used as a user I/O pin when it does not feed the nCE pin of another device.

(4) The MSEL pin settings vary for different configuration voltage standards and POR time. You must set the master device in AP mode and the slave

devices in FPP mode. To connect MSEL[3..0] for the master device in AP mode and the slave devices in FPP mode, refer to Table 9–7 on

page 9–11. Connect the MSEL pins directly to VCCA or GND.

(5) The AP configuration ignores the WAIT signal during configuration mode. However, if you are accessing flash during user mode with user logic,

you can optionally use the normal I/O pin to monitor the WAIT signal from the Micron P30 or P33 flash.

(6) Connect the repeater buffers between the Cyclone III master device and slave devices for DATA[15..0] and DCLK. All I/O inputs must maintain a

maximum AC voltage of 4.1 V. The output resistance of the repeater buffers must fit the maximum overshoot equation outlined in “Configuration

and JTAG Pin I/O Requirements” on page 9–7.

CLK

RST#

CE#

OE#

ADV#

WE#

WAIT

DQ[15:0]

A[24:1]

DCLK

nRESET

FLASH_nCE

nOE

nAVD

nWE

I/O (5)

DATA[15..0]

PADD[23..0]

nCE

VCCIO (1)

10 k

MSEL[3..0]

(4)

nCEO

N.C. (3)

Cyclone III Master Device

Micron P30/P33 Flash

GND

DATA[7..0]

DCLK

nCE

MSEL[3..0]

(4)

nCEO

Cyclone III Slave Device

DATA[7..0]

DCLK

nCE

MSEL[3..0]

(4)

nCEO

Cyclone III Slave Device

VCCIO (2)

10 k

VCCIO (2)

10 k

Buffers (6)

DQ[7..0]

N.C. (3)

DATA[7..0]

DCLK

nCE

MSEL[3..0]

(4)

nCEO

Cyclone III Slave Device

DATA[7..0]

DCLK

nCE

MSEL[3..0]

(4)

nCEO

Cyclone III Slave Device

DQ[7..0]

VCCIO (1)

DQ[15..8]

VCCIO (1)

10 k

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