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CDPCLK4 Scheda tecnica(PDF) 189 Page - Altera Corporation

Il numero della parte CDPCLK4
Spiegazioni elettronici  Cyclone III Device Handbook
PDF  274 Pages
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Produttore elettronici  ALTERA [Altera Corporation]
Homepage  http://www.altera.com
Logo ALTERA - Altera Corporation

CDPCLK4 Scheda tecnica(HTML) 189 Page - Altera Corporation

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Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
9–31
Configuration Features
August 2012
Altera Corporation
Cyclone III Device Handbook
Volume 1
Figure 9–11 shows the AP configuration with multiple bus masters.
Figure 9–11. AP Configuration with Multiple Bus Masters
Notes to Figure 9–11:
(1) Connect the pull-up resistors to the VCCIO supply of the bank in which the pin resides.
(2) The nCEO pin is left unconnected or used as a user I/O pin when it does not feed the nCE pin of another device.
(3) The MSEL pin settings vary for different configuration voltage standards and POR time. To connect MSEL[3..0], refer to Table 9–7 on page 9–11.
Connect the MSEL pins directly to VCCA or GND.
(4) The AP configuration ignores the WAIT signal during configuration mode. However, if you are accessing flash during user mode with user logic,
you can optionally use the normal I/O to monitor the WAIT signal from the Micron P30 or P33 flash.
(5) When cascading Cyclone III devices in a multi-device AP configuration, connect the repeater buffers between the master device and slave devices
for DATA[15..0] and DCLK. All I/O inputs must maintain a maximum AC voltage of 4.1 V. The output resistance of the repeater buffers must fit
the maximum overshoot equation outlined in “Configuration and JTAG Pin I/O Requirements” on page 9–7.
(6) The other master device must fit the maximum overshoot equation outlined in “Configuration and JTAG Pin I/O Requirements” on page 9–7.
(7) The other master device can control the AP configuration bus by driving the nCE pin to high with an output high on the I/O pin.
(8) The other master device can pulse nCONFIG if it is under system control rather than tied to VCCIO.
CLK
RST#
CE#
OE#
ADV#
WE#
WAIT
DQ[15:0]
A[24:1]
DCLK (5)
nRESET
FLASH_nCE
nOE
nAVD
nWE
I/O (4)
DATA[15..0] (5)
PADD[23..0]
nCE
VCCIO (1)
VCCIO (1)
10 k
10 k
MSEL[3..0]
(3)
nCEO
Cyclone III Master Device
Micron P30/P33 Flash
GND
10 k
(2)
Other Master Device (6)
VCCIO (1)
10 k



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