CDPCLK4 datasheet(212/274 Pages) ALTERA

212 / 274 page

9–54

Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family

Configuration Features

Cyclone III Device Handbook

August 2012

Altera Corporation

Volume 1

1 All I/O inputs must maintain a maximum AC voltage of 4.1 V. If a non-Cyclone III

device family is cascaded in the JTAG-chain, TDO of the non-Cyclone III device family

driving into TDI of the Cyclone III device family must fit the maximum overshoot

equation outlined in “Configuration and JTAG Pin I/O Requirements” on page 9–7.

The nCE pin must be connected to GND or driven low during JTAG configuration. In

multi-device AS, AP, PS, and FPP configuration chains, the nCE pin of the first device

is connected to GND while its nCEO pin is connected to the nCE pin of the next device

in the chain. The inputs of the nCE pin of the last device come from the previous device

while its nCEO pin is left floating. In addition, the CONF_DONE and nSTATUS signals are

shared in multi-device AS, AP, PS, and FPP configuration chains to ensure that the

devices enter user mode at the same time after configuration is complete. When the

CONF_DONE

and nSTATUS signals are shared among all the devices, every device must

be configured when you perform JTAG configuration.

If you only use JTAG configuration, Altera recommends that you connect the circuitry

as shown in Figure 9–26 or Figure 9–27, in which each of the CONF_DONE and nSTATUS

signals are isolated so that each device can enter user mode individually.

Figure 9–27. JTAG Configuration of Multiple Devices Using a Download Cable (1.2, 1.5, and 1.8-V VCCIO Powering the

JTAG Pins)

Notes to Figure 9–27:

(1) Connect these pull-up resistors to the VCCIO supply of the bank in which the pin resides.

(2) Connect the nCONFIG and MSEL[3..0] pins to support a non-JTAG configuration scheme. If you only use a JTAG configuration, connect the

nCONFIG

pin to logic high and the MSEL[3..0] pins to ground. In addition, pull DCLK and DATA[0] either high or low, whichever is convenient

on your board.

(3) In the USB-Blaster and ByteBlaster II cable, this pin is connected to nCE when it is used for AS programming, otherwise it is a no connect.

(4) The nCE pin must be connected to ground or driven low for successful JTAG configuration.

(5) Power up the VCC of the ByteBlaster II or USB-Blaster cable with supply from VCCIO. The ByteBlaster II and USB-Blaster cables do not support a

target supply voltage of 1.2 V. For the target supply voltage value, refer to the ByteBlaster II Download Cable User Guide and the USB-Blaster

Download Cable User Guide.

(6) The resistor value can vary from 1 k

 to 10 k. Perform signal integrity analysis to select the resistor value for your setup.

TMS

TCK

Download Cable

10-Pin Male Header

TDI

TDO

VCCIO (1)

VCCIO (5)

Pin 1

nST

ATUS

nCONFIG

nCE (4)

VCCIO

CONF_DONE

VCCIO

(2)

VIO

(3)

(6)

(1)

(2)

DATA[0]

DCLK

(2)

MSEL[3..0]

nCEO

(2)

TMS

TCK

TDI

TDO

nST

ATUS

nCONFIG

nCE (4)

VCCIO

CONF_DONE

VCCIO

(2)

(1)

(2)

DATA[0]

DCLK

(2)

MSEL[3..0]

nCEO

(2)

(1)

TMS

TCK

TDI

TDO

nST

ATUS

nCONFIG

nCE (4)

VCCIO

CONF_DONE

VCCIO

(2)

DATA[0]

DCLK

(2)

MSEL[3..0]

nCEO

(2)

(1)

10 k

1 k

10 k

Cyclone III

Device Family

Cyclone III

Device Family

Cyclone III

Device Family

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