CDPCLK4 datasheet(211/274 Pages) ALTERA

211 / 274 page

Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family

9–53

Configuration Features

August 2012

Altera Corporation

Cyclone III Device Handbook

Volume 1

When programming a JTAG device chain, one JTAG-compatible header is connected

to several devices. The number of devices in the JTAG chain is limited only by the

drive capability of the download cable. When four or more devices are connected in a

JTAG chain, Altera recommends buffering the TCK, TDI, and TMS pins with an on-board

buffer.

JTAG-chain device programming is ideal when the system contains multiple devices,

or when testing your system using JTAG BST circuitry. Figure 9–26 and Figure 9–27

show a multi-device JTAG configuration.

For the device VCCIO of 2.5, 3.0, and 3.3 V, refer to Figure 9–26. All I/O inputs must

maintain a maximum AC voltage of 4.1 V. Because JTAG pins do not have the internal

PCI clamping diodes to prevent voltage overshoot when using VCCIO of 2.5, 3.0, and

3.3 V, you must power up the VCC of the download cable with a 2.5-V supply from

VCCA.

For device VCCIO of 1.2, 1.5, and 1.8 V, refer to Figure 9–27. You can power up the VCC

of the download cable with the supply from VCCIO.

Figure 9–26. JTAG Configuration of Multiple Devices Using a Download Cable (2.5, 3.0, and 3.3-V VCCIO Powering the

JTAG Pins)

Notes to Figure 9–26:

(1) Connect these pull-up resistors to the VCCIO supply of the bank in which the pin resides.

(2) Connect the nCONFIG and MSEL[3..0] pins to support a non-JTAG configuration scheme. If you only use a JTAG configuration, connect the

nCONFIG

pin to logic high and the MSEL[3..0] pins to ground. In addition, pull DCLK and DATA[0] either high or low, whichever is convenient

on your board.

(3) Pin 6 of the header is a VIO reference voltage for the MasterBlaster output driver. VIO must match the VCCA of the device. For this value, refer to the

MasterBlaster Serial/USB Communications Cable User Guide. In the ByteBlasterMV cable, this pin is a no connect. In the USB-Blaster and

ByteBlaster II cables, this pin is connected to nCE when it is used for AS programming, otherwise it is a no connect.

(4) The nCE pin must be connected to ground or driven low for successful JTAG configuration.

(5) Power up the VCC of the ByteBlaster II, USB-Blaster, or ByteBlasterMV cable with a 2.5- V supply from VCCA. Third-party programmers must switch

to 2.5 V. Pin 4 of the header is a VCC power supply for the MasterBlaster cable. The MasterBlaster cable can receive power from either 5.0- or 3.3-V

circuit boards, DC power supply, or 5.0 V from the USB cable. For this value, refer to the MasterBlaster Serial/USB Communications User Guide.

(6) The resistor value can vary from 1 k

 to 10 k. Perform signal integrity analysis to select the resistor value for your setup.

TMS

TCK

Download Cable

10-Pin Male Header

TDI

TDO

VCCA

VCCA (5)

Pin 1

nST

ATUS

nCONFIG

nCE (4)

VCCIO

CONF_DONE

VCCIO

(2)

VIO

(3)

(1)

(2)

DATA[0]

DCLK

(2)

MSEL[3..0]

nCEO

(2)

TMS

TCK

TDI

TDO

nST

ATUS

nCONFIG

nCE (4)

VCCIO

CONF_DONE

VCCIO

(2)

(1)

(2)

DATA[0]

DCLK

(2)

MSEL[3..0]

nCEO

(2)

(1)

TMS

TCK

TDI

TDO

nST

ATUS

nCONFIG

nCE (4)

VCCIO

CONF_DONE

VCCIO

(2)

DATA[0]

DCLK

(2)

MSEL[3..0]

nCEO

(2)

(1)

10 k

(6)

1 k

10 k

Cyclone III Device

Family

Cyclone III Device

Family

Cyclone III Device

Family

CDPCLK4 Scheda tecnica(PDF) 211 Page - Altera Corporation

CDPCLK4 Scheda tecnica(HTML) 211 Page - Altera Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Scheda tecnica Scarica

Link URL