CDPCLK4 datasheet(217/274 Pages) ALTERA

217 / 274 page

Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family

9–59

Configuration Features

August 2012

Altera Corporation

Cyclone III Device Handbook

Volume 1

If you configure a master device with a SFL design, the master device enters user

mode even though the slave devices in the multiple device chain are not being

configured. The master device enters user mode with a SFL design even though the

CONF_DONE

signal is externally held low by the other slave devices in chain.

Figure 9–30 shows the JTAG configuration of a single Cyclone III device family with a

SFL design.

ISP of the Configuration Device

In the second stage, the SFL design in the master device allows you to write the

configuration data for the device chain into the serial configuration device with the

Cyclone III device family JTAG interface. The JTAG interface sends the programming

data for the serial configuration device to the Cyclone III device family first. The

Cyclone III device family then uses the ASMI pins to send the data to the serial

configuration device.

Figure 9–30. Programming Serial Configuration Devices In-System Using the JTAG Interface

Notes to Figure 9–30:

(1) Connect the pull-up resistors to the VCCIO supply of the bank in which the pin resides.

(2) The MSEL pin settings vary for different configuration voltage standards and POR time. To connect MSEL[3..0]for

AS configuration schemes, refer to Table 9–7 on page 9–11. Connect the MSEL pins directly to VCCA or GND.

(3) Pin 6 of the header is a VIO reference voltage for the MasterBlaster output driver. VIO must match the VCCA of the

device. For this value, refer to the MasterBlaster Serial/USB Communications Cable User Guide. In ByteBlasterMV,

this pin is a no connect. In USB-Blaster, ByteBlaster II, and Ethernet Blaster, this pin is connected to nCE when it is

used for AS programming, otherwise it is a no connect.

(4) The nCE pin must be connected to GND or driven low for successful JTAG configuration.

(5) The nCEO pin is left unconnected or used as a user I/O pin when it does not feed the nCE pin of another device.

(6) Power up the VCC of the ByteBlaster II, USB-Blaster, ByteBlasterMV, or Ethernet Blaster cable with a 2.5-V supply from

VCCA. Third-party programmers must switch to 2.5 V. Pin 4 of the header is a VCC power supply for the MasterBlaster

cable. The MasterBlaster cable can receive power from either 5.0- or 3.3-V circuit boards, DC power supply, or 5.0 V

from the USB cable. For this value, refer to the MasterBlaster Serial/USB Communications Cable User Guide.

(7) Connect the series resistor at the near end of the serial configuration device.

(8) These are dual-purpose I/O pins. The nCSO pin functions as the FLASH_NCE pin in AP mode. The ASDO pin functions

as the DATA[1] pin in other AP and FPP modes.

(9) The resistor value can vary from 1 k

 to 10 k. Perform signal integrity analysis to select the resistor value for your

setup.

nCE (4)

MSEL[3..0]

nCONFIG

CONF_DONE

VCCA

VCCA (6)

GND

VCCIO (1)

GND

VCCIO (1)

(2)

VCCA

10 k

(9)

nSTATUS

Pin 1

Download Cable 10-Pin Male

Header (Top View)

GND

TCK

TDO

TMS

TDI

1 k

GND

VIO (3)

Cyclone III Device Family

nCEO

N.C. (5)

DCLK

DATA[0]

nCSO (8)

ASDO (8)

DCLK

DATA

nCS

ASDI

Serial Configuration

Device

VCCIO (1)

10 k

Serial

Flash

Loader

Ω (7)

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