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CIII51014-2.3

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Cyclone III Device Handbook

Volume 1

December 2011

ISO

9001:2008

Registered

12. IEEE 1149.1 (JTAG) Boundary-Scan

Testing for the Cyclone III Device Family

This chapter provides guidelines on using the IEEE Std. 1149.1 boundary-scan test

(BST) circuitry in Cyclone® III device family (Cyclone III and Cyclone III LS devices).

BST architecture tests pin connections without using physical test probes, and

captures functional data while a device is operating normally. Boundary-scan cells

(BSCs) in a device can force signals onto pins or capture data from pin or logic array

signals. Forced test data is serially shifted into the boundary-scan cells. Captured data

is serially shifted out and externally compared to expected results.

This chapter contains the following sections:

■

“IEEE Std. 1149.1 BST Architecture” on page 12–1

■

“IEEE Std. 1149.1 BST Operation Control” on page 12–2

■

“I/O Voltage Support in a JTAG Chain” on page 12–5

■

“Guidelines for IEEE Std. 1149.1 BST” on page 12–6

■

“Boundary-Scan Description Language Support” on page 12–7

IEEE Std. 1149.1 BST Architecture

Cyclone III device family operating in the IEEE Std. 1149.1 BST mode use four

required pins:

■

TDI

■

TDO

■

TMS

■

TCK

The TCK pin has an internal weak pull-down resistor, while the TDI and TMS pins have

weak internal pull-up resistors. The TDO output pin and all the JTAG input pins are

configuration.

1 For recommendations on how to connect a JTAG chain with multiple voltages across

the devices in the chain, refer to “I/O Voltage Support in a JTAG Chain” on page 12–5.

f For more information about the description and functionality of all JTAG pins,

registers used by the IEEE Std. 1149.1 BST circuitry, and the test access port (TAP)

controller, refer to AN39: IEEE 1149.1 (JTAG) Boundary-Scan Testing in Altera Devices.

December 2011

CIII51014-2.3

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