CDPCLK4 datasheet(262/274 Pages) ALTERA

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11–10

Chapter 11: SEU Mitigation in the Cyclone III Device Family

Recovering from CRC Errors

Cyclone III Device Handbook

December 2011

Altera Corporation

Volume 1

Recovering from CRC Errors

The system that the Altera FPGA resides in must control device reconfiguration. After

detecting an error on the CRC_ERROR pin, strobing the nCONFIG low directs the system

to perform the reconfiguration at a time when it is safe for the system to reconfigure

the FPGA.

When the data bit is rewritten with the correct value by reconfiguring the device, the

device functions correctly.

While soft errors are uncommon in Altera devices, certain high-reliability applications

might require a design to account for these errors.

Document Revision History

Table 11–9 lists the revision history for this document.

.ldsrc

(<ldsrc

source>)

Input

This signal is an input into the error detection block. If ldsrc=0, the

pre-computed CRC register is selected for loading into the 32-bit shift register

at the rising edge of clk when shiftnld=0. If ldsrc=1, the signature

when shiftnld=1. This port is required.

.crcerror

(<crcerror

indicator

output>)

Output

This signal is the output of the cell that is synchronized to the internal

oscillator of the device (80-MHz internal oscillator) and not to the clk port. It

asserts high if the error block detects that a SRAM bit has flipped and the

internal CRC computation has shown a difference with respect to the pre-

computed value. This signal must be connected either to an output pin or a

bidirectional pin. If it is connected to an output pin, you can only monitor the

CRC_ERROR pin

(the core cannot access this output). If the CRC_ERROR

signal is used by core logic to read error detection logic, this signal must be

connected to a BIDIR pin. The signal is fed to the core indirectly by feeding a

BIDIR

pin that has its output enable port connected to VCC (Figure 11–3 on

page 11–8).

.regout

(<registered

output>)

Output

This signal is the output of the error detection shift register synchronized to

the clk port, to be read by core logic. It shifts one bit at each cycle, so you

should clock the clk signal 31 cycles to read out the 32 bits of the shift

.cyclecomplete (<cyclone

complete indicator

output>)

Output

This signal is for cycloneiiils_crcblock only. This output signal is

synchronized to the internal oscillator of the device (80-MHz internal

oscillator), and not to the clk port. The signal asserts high for one clock

cyclone every time an error detection cyclone completes.

Table 11–8. CRC Block Input and Output Ports

(Part 2 of 2)

Port

Input/Output

Definition

Table 11–9. Document Revision History (Part 1 of 2)

Date

Version

Changes

December 2011

2.3

■ Updated “User Mode Error Detection” on page 11–2.

■ Update hyperlinks.

■ Minor text edits.

December 2009

2.2

Minor changes to the text.

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