CDPCLK4 datasheet(261/274 Pages) ALTERA

261 / 274 page

Chapter 11: SEU Mitigation in the Cyclone III Device Family

11–9

Software Support

December 2011

Altera Corporation

Cyclone III Device Handbook

Volume 1

Table 11–7 lists the name of the WYSIWYG atom for Cyclone III device family.

1 To enable the cycloneiii_crcblock primitive in version 8.0 SP1 or earlier of the

Quartus II software, turn on the error detection CRC feature in the Device and Pins

Options

dialog box. This is not required when you are using version 8.1 and later of

the Quartus II software.

Example 11–1 shows an example of how to define the input and output ports of a

WYSIWYG atom in a Cyclone III LS device.

Table 11–8 lists the input and output ports that must be included in the atom. The

input and output ports of the atoms for Cyclone III device family are similar, except

for the cyclecomplete port which is for Cyclone III LS devices only.

Table 11–7. WYSIWYG Atoms

Device

WYSIWYG Atom

Cyclone III

cycloneiii_crcblock

Cyclone III LS

cycloneiiils_crcblock

Example 11–1. Error Detection Block Diagram

cycloneiiils_crcblock<crcblock_name>

(

.clk(<clock source>),

.shiftnld(<shiftnld source>),

.ldsrc(<ldsrc source>),

.crcerror(<crcerror out destination>),

.regout(<output destination>),

.cyclecomplete(<cyclecomplete destination>),

);

Table 11–8. CRC Block Input and Output Ports

(Part 1 of 2)

Port

Input/Output

Definition

<crcblock_name>

Input

Unique identifier for the CRC block, and represents any identifier name that is

legal for the given description language (For example Verilog HDL, VHDL,

AHDL). This field is required.

.clk(<clock source>

Input

This signal designates the clock input of this cell. All operations of this cell are

with respect to the rising edge of the clock. Whether it is the loading of the

data into the cell or data out of the cell, it always occurs on the rising edge.

This port is required.

.shiftnld

(<shiftnld

source>)

Input

This signal is an input into the error detection block. If shiftnld=1, the

data is shifted from the internal shift register to the regout at each rising edge

of clk. If shiftnld=0, the shift register parallel loads either the

pre-calculated CRC value or the update register contents depending on the

ldsrc

port input. This port is required.

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