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CY8C52LP Scheda tecnica(PDF) 39 Page - Cypress Semiconductor

Il numero della parte CY8C52LP
Spiegazioni elettronici  Programmable System-on-Chip (PSoC짰)
PDF  114 Pages
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Produttore elettronici  CYPRESS [Cypress Semiconductor]
Homepage  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY8C52LP Scheda tecnica(HTML) 39 Page - Cypress Semiconductor

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PSoC® 5LP: CY8C52LP Family
Datasheet
Document Number: 001-84933 Rev. *L
Page 39 of 114
7. Digital Subsystem
The digital programmable system creates application specific
combinations of both standard and advanced digital peripherals
and custom logic functions. These peripherals and logic are then
interconnected to each other and to any pin on the device,
providing a high level of design flexibility and IP security.
The features of the digital programmable system are outlined
here to provide an overview of capabilities and architecture. You
do not need to interact directly with the programmable digital
system at the hardware and register level. PSoC Creator
provides a high level schematic capture graphical interface to
automatically place and route resources similar to PLDs.
The main components of the digital programmable system are:
Universal digital blocks (UDB) - These form the core
functionality of the digital programmable system. UDBs are a
collection of uncommitted logic (PLD) and structural logic
(Datapath) optimized to create all common embedded
peripherals and customized functionality that are application or
design specific.
Universal digital block array - UDB blocks are arrayed within a
matrix of programmable interconnect. The UDB array structure
is homogeneous and allows for flexible mapping of digital
functions onto the array. The array supports extensive and
flexible routing interconnects between UDBs and the digital
system interconnect.
Digital system interconnect (DSI) - Digital signals from UDBs,
fixed function peripherals, I/O pins, interrupts, DMA, and other
system core signals are attached to the DSI to implement full
featured device connectivity. The DSI allows any digital function
to any pin or other feature routability when used with the UDB
array.
Figure 7-1. CY8C52LP Digital Programmable Architecture
7.1 Example Peripherals
The flexibility of the CY8C52LP family’s UDBs and analog blocks
allow you to create a wide range of components (peripherals).
The most common peripherals were built and characterized by
Cypress and are shown in the PSoC Creator component catalog.
However, you may also create your own custom components
using PSoC Creator. Using PSoC Creator, you may also create
their own components for reuse within their organization, for
example sensor interfaces, proprietary algorithms, and display
interfaces.
The number of components available through PSoC Creator is
too numerous to list in the datasheet, and the list is always
growing. An example of a component available for use in
CY8C52LP family, but, not explicitly called out in this datasheet
is the UART component.
7.1.1 Example Digital Components
The following is a sample of the digital components available in
PSoC Creator for the CY8C52LP family. The exact amount of
hardware resources (UDBs, routing, RAM, flash) used by a
component varies with the features selected in PSoC Creator for
the component.
Communications
I2C
UART
SPI
Functions
EMIF
PWMs
Timers
Counters
Logic
NOT
OR
XOR
AND
7.1.2 Example Analog Components
The following is a sample of the analog components available in
PSoC Creator for the CY8C52LP family. The exact amount of
hardware resources (SC/CT blocks, routing, RAM, flash) used
by a component varies with the features selected in PSoC
Creator for the component.
ADC
Successive Approximation (SAR ADC)
DACs
Current
Voltage
PWM
Comparators
Digital Core System
and Fixed Function Peripherals
DSI Routing Interface
DSI Routing Interface
Digital Core System
and Fixed Function Peripherals
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB



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