CY8C52LP datasheet(99/114 Pages) CYPRESS

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PSoC® 5LP: CY8C52LP Family

Datasheet

Document Number: 001-84933 Rev. *L

Page 99 of 114

11.8.5 SWD Interface

Figure 11-61. SWD Interface Timing

11.8.6 TPIU Interface

SW DIO

(P SoC input)

SW DCK

T_SW D I_setup

SW DIO

(PSoC output)

(1/f_SW DCK)

T_SW D I_hold

T_SW D O _valid

T_SW D O _hold

Table 11-58. SWD Interface AC Specifications[74]

Parameter

Description

Conditions

Min

Typ

Max

Units

f_SWDCK

SWDCLK frequency

3.3 V

 VDDD  5V

–

12[75]

MHz

1.71 V

 VDDD < 3.3 V

–

7[75]

MHz

1.71 V

 VDDD < 3.3 V, SWD over

USBIO pins

––

5.5[75]

MHz

T_SWDI_setup SWDIO input setup before SWDCK high T = 1/f_SWDCK max

T/4

–

T_SWDI_hold

SWDIO input hold after SWDCK high

T = 1/f_SWDCK max

T/4

–

T_SWDO_valid SWDCK high to SWDIO output

T = 1/f_SWDCK max

–

T/2

T_SWDO_hold SWDIO output hold after SWDCK high T = 1/f_SWDCK max

–

Notes

74. Based on device characterization (Not production tested).

75. f_SWDCK must also be no more than 1/3 CPU clock frequency.

76. TRACEPORT signal frequency and bit rate are limited by GPIO output frequency, see Table 11-9 on page 69.

Table 11-59. TPIU Interface AC Specifications[74]

Parameter

Description

Conditions

Min

Typ

Max

Units

TRACEPORT (TRACECLK) frequency

–

33[76]

MHz

SWV bit rate

–

33[76]

Mbit

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