CY8C52LP datasheet(96/114 Pages) CYPRESS

96 / 114 page

PSoC® 5LP: CY8C52LP Family

Datasheet

Document Number: 001-84933 Rev. *L

Page 96 of 114

Figure 11-59. Synchronous Write and Read Cycle Timing, No Wait States

Table 11-51. Synchronous Write and Read Timing Specifications[66]

Parameter

Description

Conditions

Min

Typ

Max

Units

Fbus_clock Bus clock frequency[67]

––

MHz

Tbus_clock Bus clock period[68]

30.3

–

Twr_Setup

Time from EM_data valid to rising edge of

EM_Clock

Tbus_clock – 10

–

Trd_setup

Time that EM_data must be valid before rising

edge of EM_OE

5–

–

Trd_hold

Time that EM_data must be valid after rising

edge of EM_OE

5–

–

Tbus_clock

Bus Clock

EM_Addr

EM_CE

EM_ADSC

EM_Clock

EM_WE

EM_OE

EM_Data

Trd_setup

Trd_hold

Write Cycle

Read Cycle

Minimum of 4 bus clock cycles between successive EMIF accesses

Twr_setup

Notes

66. Based on device characterization (Not production tested).

67. EMIF signal timings are limited by GPIO frequency limitations. See “GPIO” section on page 68.

68. EMIF output signals are generally synchronized to bus clock, so EMIF signal timings are dependent on bus clock frequency.

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