CY8C52LP datasheet(76/114 Pages) CYPRESS

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PSoC® 5LP: CY8C52LP Family

Datasheet

Document Number: 001-84933 Rev. *L

Page 76 of 114

11.5.2 SAR ADC

Figure 11-25. SAR ADC DNL vs Output Code,

Bypassed Internal Reference Mode

Figure 11-26. SAR ADC INL vs Output Code,

Bypassed Internal Reference Mode

Table 11-19. SAR ADC DC Specifications

Parameter

Description

Conditions

Min

Typ

Max

Units

Resolution

–

bits

Number of channels – single-ended

–

No of

GPIO

Number of channels – differential

Differential pair is formed using a

pair of neighboring GPIO.

––

No of

GPIO/2

Monotonicity[40]

Yes

–

Gain error[41]

External reference

–

±0.1

VOS

Input offset voltage

–

±2

IDD

Current consumption[40]

––

Input voltage range – single-ended[40]

VSSA

–VDDA

Input voltage range – differential[40]

VSSA

–VDDA

PSRR

Power supply rejection ratio[40]

–

CMRR

Common mode rejection ratio

–

INL

Integral non linearity[40]

VDDA 1.71 to 5.5 V, 1 Msps, VREF

1 to 5.5 V, bypassed at ExtRef pin

––

+2/–1.5

LSB

VDDA 2.0 to 3.6 V, 1 Msps, VREF

2 to VDDA, bypassed at ExtRef pin

––

±1.2

LSB

VDDA 1.71 to 5.5 V, 500 ksps,

VREF 1 to 5.5 V, bypassed at

ExtRef pin

––

±1.3

LSB

DNL

Differential non linearity[40]

VDDA 1.71 to 5.5 V, 1 Msps, VREF

1 to 5.5 V, bypassed at ExtRef pin

––

+2/–1

LSB

VDDA 2.0 to 3.6 V, 1 Msps, VREF

2 to VDDA, bypassed at ExtRef pin

No missing codes

––

1.7/–0.99

LSB

VDDA 1.71 to 5.5 V, 500 ksps,

VREF 1 to 5.5 V, bypassed at

ExtRef pin

No missing codes

–

+2/–0.99

LSB

RIN

Input resistance[40]

–180

–

kΩ

Notes

40. Based on device characterization (Not production tested).

41. For total analog system Idd < 5 mA, depending on package used. With higher total analog system currents it is recommended that the SAR ADC be used in differential

mode.

0.5

-1

-0.5

-2048

2048

Code (12 bit)

0.5

-1

-0.5

-2048

2048

Code (12 bit)

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