CY8C52LP datasheet(92/114 Pages) CYPRESS

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PSoC® 5LP: CY8C52LP Family

Datasheet

Document Number: 001-84933 Rev. *L

Page 92 of 114

11.6.6 Universal Digital Blocks (UDBs)

PSoC Creator provides a library of pre-built and tested standard digital peripherals (UART, SPI, LIN, PRS, CRC, timer, counter, PWM,

AND, OR, and so on) that are mapped to the UDB array. See the component datasheets in PSoC Creator for full AC/DC specifications,

APIs, and example code.

Figure 11-57. Clock to Output Performance

Note

60. Based on device characterization (Not production tested).

Table 11-41. UDB AC Specifications[60]

Parameter

Description

Conditions

Min

Typ

Max

Units

Datapath Performance

FMAX_TIMER Maximum frequency of 16-bit timer in

a UDB pair

–

67.01

MHz

FMAX_ADDER Maximum frequency of 16-bit adder in

a UDB pair

–

67.01

MHz

FMAX_CRC

Maximum frequency of 16-bit

CRC/PRS in a UDB pair

–

67.01

MHz

PLD Performance

FMAX_PLD

Maximum frequency of a two-pass

PLD function in a UDB pair

–

67.01

MHz

Clock to Output Performance

tCLK_OUT

Propagation delay for clock in to data

out, see Figure 11-57.

25 °C, VDDD  2.7 V

–

tCLK_OUT

Propagation delay for clock in to data

out, see Figure 11-57.

Worst-case placement, routing,

and pin selection

–

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