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CY8C52LP Scheda tecnica(PDF) 79 Page - Cypress Semiconductor |
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CY8C52LP Scheda tecnica(HTML) 79 Page - Cypress Semiconductor |
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79 / 114 page ![]() PSoC® 5LP: CY8C52LP Family Datasheet Document Number: 001-84933 Rev. *L Page 79 of 114 11.5.4 Comparator Notes 46. The recommended procedure for using a custom trim value for the on-chip comparators are found in the TRM. 47. Based on device characterization (Not production tested). Table 11-23. Comparator DC Specifications[46, 47] Parameter Description Conditions Min Typ Max Units VOS Input offset voltage in fast mode Factory trim, VDDA > 2.7 V, VIN 0.5 V –10 mV Input offset voltage in slow mode Factory trim, VIN 0.5 V – 9 mV VOS Input offset voltage in fast mode Custom trim – – 4 mV Input offset voltage in slow mode Custom trim – – 4 mV VOS Input offset voltage in ultra low power mode –±12 – mV TCVos Temperature coefficient, input offset voltage VCM = VDDA / 2, fast mode – 63 85 µV/°C VCM = VDDA / 2, slow mode – 15 20 VHYST Hysteresis Hysteresis enable mode – 10 32 mV VICM Input common mode voltage High current / fast mode VSSA –VDDA V Low current / slow mode VSSA –VDDA V Ultra low power mode VSSA –VDDA – 1.15 V CMRR Common mode rejection ratio – 50 – dB ICMP High current mode/fast mode – – 400 µA Low current mode/slow mode – – 100 µA Ultra low power mode – 6 – µA Table 11-24. Comparator AC Specifications[46, 47] Parameter Description Conditions Min Typ Max Units TRESP Response time, high current mode 50 mV overdrive, measured pin-to-pin – 75 110 ns Response time, low current mode 50 mV overdrive, measured pin-to-pin – 155 200 ns Response time, ultra low power mode 50 mV overdrive, measured pin-to-pin –55 – µs |
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