CY8C52LP datasheet(21/114 Pages) CYPRESS

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PSoC® 5LP: CY8C52LP Family

Datasheet

Document Number: 001-84933 Rev. *L

Page 21 of 114

5.6 External Memory Interface

CY8C52LP provides an External Memory Interface (EMIF) for

connecting to external memory devices. The connection allows

read and write accesses to external memories. The EMIF

operates in conjunction with UDBs, I/O ports, and other

hardware to generate external memory address and control

signals. At 33 MHz, each memory access cycle takes four bus

clock cycles.

Figure 5-1 is the EMIF block diagram. The EMIF supports

synchronous and asynchronous memories. The CY8C52LP only

supports one type of external memory device at a time.

External memory is located in the Cortex-M3 external RAM

space; it can use up to 24 address bits. See Table 5-4 on page

22 and Memory Map on page 22. The memory can be 8 or 16

bits wide.

Cortex-M3 instructions can be fetched from external memory if it

is 16-bit. Other limitations apply; for details, see application note

AN89610, PSoC® 4 and PSoC 5LP ARM Cortex Code

Optimization. There is no provision for code security in external

memory. If code must be kept secure, then it should be placed in

internal flash. See Flash Security on page 19 and Device

Security on page 58.

Figure 5-1. EMIF Block Diagram

PHUB

IO IF

UDB

EMIF

I/O

PORTs

I/O

PORTs

I/O

PORTs

Data,

Address,

and Control

Signals

Data,

Address,

and Control

Signals

Address Signals

Data Signals

Control Signals

Data,

Address,

and Control

Signals

EM Control

Signals

Other

Control

Signals

DSI Dynamic Output

Control

DSI to Port

Control

External_ MEM_ DATA[15:0]

External_ MEM_ ADDR[23:0]

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