CY8C52LP datasheet(98/114 Pages) CYPRESS

98 / 114 page

PSoC® 5LP: CY8C52LP Family

Datasheet

Document Number: 001-84933 Rev. *L

Page 98 of 114

11.8.3 Interrupt Controller

11.8.4 JTAG Interface

Figure 11-60. JTAG Interface Timing

Notes

71. ARM Cortex-M3 NVIC spec. Visit www.arm.com for detailed documentation about the Cortex-M3 CPU.

72. Based on device characterization (Not production tested).

73. f_TCK must also be no more than 1/3 CPU clock frequency.

Table 11-56. Interrupt Controller AC Specifications

Parameter

Description

Conditions

Min

Typ

Max

Units

Delay from interrupt signal input to ISR

code execution from main line code[71]

–

Tcy CPU

Delay from interrupt signal input to ISR

code execution from ISR code

(tail-chaining)[71]

–

Tcy CPU

Table 11-57. JTAG Interface AC Specifications[72]

Parameter

Description

Conditions

Min

Typ

Max

Units

f_TCK

TCK frequency

3.3 V

 VDDD  5V

–

12[73]

MHz

1.71 V

 VDDD < 3.3 V

–

7[73]

MHz

T_TDI_setup

TDI setup before TCK high

(T/10) – 5

–

T_TMS_setup

TMS setup before TCK high

T/4

–

T_TDI_hold

TDI, TMS hold after TCK high

T = 1/f_TCK max

T/4

–

T_TDO_valid

TCK low to TDO valid

T = 1/f_TCK max

–

2T/5

T_TDO_hold

TDO hold after TCK high

T = 1/f_TCK max

T/4

–

T_nTRST

Minimum nTRST pulse width

f_TCK = 2 MHz

–

TDI

TCK

T_TDI_setup

TDO

(1/f_TCK)

T_TDI_hold

T_TDO_valid

T_TDO_hold

TMS

T_TMS_setup T_TMS_hold

CY8C52LP Scheda tecnica(PDF) 98 Page - Cypress Semiconductor

CY8C52LP Scheda tecnica(HTML) 98 Page - Cypress Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Scheda tecnica Scarica

Link URL