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EP9312 Scheda tecnica(PDF) 59 Page - Cirrus Logic |
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EP9312 Scheda tecnica(HTML) 59 Page - Cirrus Logic |
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59 / 62 page  DS515PP7 ©Copyright 2005 Cirrus Logic (All Rights Reserved) 59 EP9312 Universal Platform SOC Processor . Table S. Pin Descriptions Pin Name Block Pad Type Pull Type Description TCK JTAG I PD JTAG clock in TDI JTAG I PD JTAG data in TDO JTAG 4ma JTAG data out TMS JTAG I PD JTAG test mode select TRSTn JTAG I PD JTAG reset BOOT[1:0] System I PD Boot mode select in XTALI PLL A Main oscillator input XTALO PLL A Main oscillator output VDD_PLL PLL P Main oscillator power, 1.8V GND_PLL PLL G Main oscillator ground RTCXTALI RTC A RTC oscillator input RTCXTALO RTC A RTC oscillator output WRn PBUS 4ma SRAM Write strobe out RDn PBUS 4ma SRAM Read / OE strobe out WAITn PBUS I PU SRAM Wait in AD[25:0] PBUS 8ma Shared Address bus out DA[31:0] PBUS 8ma PU Shared Data bus in/out CSn[3:0] PBUS 4ma PU Chip select out CSn[7:6] PBUS 4ma PU Chip select out DQMn[3:0] PBUS 8ma Shared data mask out SDCLK SDRAM 8ma SDRAM clock out SDCLKEN SDRAM 8ma SDRAM clock enable out SDCSn[3:0] SDRAM 4ma SDRAM chip selects out RASn SDRAM 8ma SDRAM RAS out CASn SDRAM 8ma SDRAM CAS out SDWEn SDRAM 8ma SDRAM write enable out P[17:0] Raster 4ma PU Pixel data bus out SPCLK Raster 12ma PU Pixel clock in/out HSYNC Raster 8ma PU Horizontal synchronization / line pulse out V_CSYNC Raster 8ma PU Vertical or composite synchronization / frame pulse out BLANK Raster 8ma PU Composite blanking signal out BRIGHT Raster 4ma PWM brightness control out PWMOUT PWM 8ma Pulse width modulator output Xp, Xm ADC A Touchscreen ADC X axis Yp, Ym ADC A Touchscreen ADC Y axis sXp, sXm ADC A Touchscreen ADC X axis feedback sYp, sYm ADC A Touchscreen ADC Y axis feedback VDD_ADC ADC P Touchscreen ADC power, 3.3V GND_ADC ADC G Touchscreen ADC ground COL[7:0] Key 8ma PU Key matrix column inputs ROW[7:0] Key 8ma PU Key matrix row outputs USBp[2:0] USB A USB positive signals USBm[2:0] USB A USB negative signals TXD0 UART1 4ma Transmit out RXD0 UART1 I PU Receive in CTSn UART1 I PU Clear to send / transmit enable DSRn UART1 I PU Data set ready / Data Carrier Detect DTRn UART1 4ma Data Terminal Ready output RTSn UART1 4ma Ready to send TXD1 UART2 4ma Transmit / IrDA output RXD1 UART2 I PU Receive / IrDA input TXD2 UART3 4ma Transmit RXD2 UART3 I PU Receive MDC EMAC 4ma Management data clock MDIO EMAC 4ma PU Management data input/output RXCLK EMAC I PD Receive clock in MIIRXD[3:0] EMAC I PD Receive data in RXDVAL EMAC I PD Receive data valid RXERR EMAC I PD Receive data error TXCLK EMAC 4ma PU Transmit clock in MIITXD[3:0] EMAC I PD Transmit data out TXEN EMAC 4ma PD Transmit enable TXERR EMAC 4ma PD Transmit error CRS EMAC I PD Carrier sense CLD EMAC I PU Collision detect GRLED LED 12ma Green LED RDLED LED 12ma Red LED EECLK EEPROM 4ma PU EEPROM / Two-wire Interface clock EEDAT EEPROM 4ma PU EEPROM / Two-wire Interface data ABITCLK AC97 8ma PD AC97 bit clock ASYNC AC97 8ma PD AC97 frame sync ASDI AC97 I PD AC97 Primary input ASDO AC97 8ma PU AC97 output ARSTn AC97 8ma AC97 reset SCLK1 SPI1 8ma PD SPI bit clock SFRM1 SPI1 8ma PD SPI Frame Clock SSPRX1 SPI1 I PD SPI input SSPTX1 SPI1 8ma SPI output INT[3:0] INT I PD External interrupts PRSTn Syscon I PU Power on reset RSTOn Syscon 4ma User Reset in out - open drain SLA[1:0] EEPROM 4ma Flash programming voltage control EGPIO[15:0] GPIO I/O, 4ma PU Enhanced GPIO DD[15:8] IDE 8ma PU IDE data bus DD7 IDE 8ma PD IDE data bus DD[6:0] IDE 8ma PU IDE data bus IDEDA[2:0] IDE 8ma IDE Device address output IDECS0n IDE 8ma IDE Chip Select 0 output IDECS1n IDE 8ma IDE Chip Select 1 output DIORn IDE 8ma IDE Read strobe output DIOWn IDE 8ma IDE Write strobe output DMACKn IDE 8ma IDE DMA acknowledge output IORDY IDE I PU IDE ready input CVDD Power P Digital power, 1.8V RVDD Power P Digital power, 3.3V CGND Ground G Digital ground RGND Ground G Digital ground Table S. Pin Descriptions (Continued) Pin Name Block Pad Type Pull Type Description |
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