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EP9312 Scheda tecnica(PDF) 36 Page - Cirrus Logic |
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EP9312 Scheda tecnica(HTML) 36 Page - Cirrus Logic |
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36 / 62 page ![]() 36 ©Copyright 2005 Cirrus Logic (All Rights Reserved) DS515PP7 EP9312 Universal Platform SOC Processor Note: DD (15:0) and DSTROBE signals are shown at both the host and the device to emphasize that cable settling time as well as cable propagation delay shall not allow the data signals to be considered stable at the host until some time after they are driven by the device. Figure 20. Sustained Ultra DMA data-in Burst Figure 21. Host Pausing an Ultra DMA data-in Burst DSTROBE (device) DD (15:0) (device) DSTROBE (host) DD (15:0) (host) t CYCRD t 2CYCRD t 2CYCRD t CYCRD t DVH t DVS t DVH t DVS t DVH t DH t DS t DS t DH t DH DD(15:0) (device) DSTROBE (device) HDMARDYn (host) STOP (host) DMACKn (host) DMARQ (device) t RP t SR t RFS |
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