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EP9312 Scheda tecnica(PDF) 27 Page - Cirrus Logic |
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EP9312 Scheda tecnica(HTML) 27 Page - Cirrus Logic |
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27 / 62 page ![]() DS515PP7 ©Copyright 2005 Cirrus Logic (All Rights Reserved) 27 EP9312 Universal Platform SOC Processor Static Memory Single Read Wait Cycle Parameter Symbol Min Typ Max Unit CSn assert to WAIT time tWAITd -- tHCLK × (WST1-2) ns WAIT assert time tWAITpw tHCLK × 2 - tHCLK × 510 ns WAIT to CSn deassert delay time tCSnd tHCLK × 3 - tHCLK × 5 ns Figure 14. Static Memory Single Read Wait Cycle Timing Measurement CSn WRn RDn DQMn AD DA WAIT t WAITpw t WAITd t CSnd |
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