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EP9312 Scheda tecnica(PDF) 60 Page - Cirrus Logic

Il numero della parte EP9312
Spiegazioni elettronici  Universal Platform System-on-chip Processor
PDF  62 Pages
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Produttore elettronici  CIRRUS [Cirrus Logic]
Homepage  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

EP9312 Scheda tecnica(HTML) 60 Page - Cirrus Logic

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©Copyright 2005 Cirrus Logic (All Rights Reserved)
DS515PP7
EP9312
Universal Platform SOC Processor
Table T illustrates the pin signal multiplexing and configuration options.
Table T. Pin Multiplex Usage Information
Physical
Pin Name
Description
Multiplex signal name
COL[7:0]
GPIO
GPIO Port D[7:0]
ROW[7:0]
GPIO
GPIO Port C[7:0]
EGPIO[0]
Ring Indicator Input
RI
EGPIO[1]
1Hz clock monitor
CLK1HZ
EGPIO[2]
IDE DMA request
DMARQ
EGPIO[3]
Transmit Enable output / HDLC clocks
TENn / HDLCCLK1 / HDLCCLK3
EGPIO[4]
I2S Transmit Data 1
SDO1
EGPIO[5]
I2S Receive Data 1
SDI1
EGPIO[6]
I2S Transmit Data 2
SDO2
EGPIO[7]
DMA Request 0
DREQ0
EGPIO[8]
DMA Acknowledge 0
DACK0
EGPIO[9]
DMA EOT 0
DEOT0
EGPIO[10]
DMA Request 1
DREQ1
EGPIO[11]
DMA Acknowledge 1
DACK1
EGPIO[12]
DMA EOT 1
DEOT1
EGPIO[13]
I2S Receive Data 2
SDI2
EGPIO[14]
PWM 1 output
PWMOUT1
EGPIO[15]
IDE Device active / present
DASP
ABITCLK
I2S Serial clock
SCLK
ASYNC
I2S Frame Clock
LRCK
ASDO
I2S Transmit Data 0
SDO0
ASDI
I2S Receive Data 0
SDI0
ARSTn
I2S Master clock
MCLK
SCLK1
I2S Serial clock
SCLK
SFRM1
I2S Frame Clock
LRCK
SSPTX1
I2S Transmit Data 0
SDO0
SSPRX1
I2S Receive Data 0
SDI0
IDEDA[2:0]
GPIO
GPIO Port E[7:5]
IDECS0n
GPIO
GPIO Port E[4]
IDECS1n
GPIO
GPIO Port E[3]
DIORn
GPIO
GPIO Port E[2]
DD[7:0]
GPIO
GPIO Port H[7:0]
DD[15:12]
GPIO
GPIO Port G[7:4]
SLA[1:0]
GPIO
GPIO Port G[3:2]
EEDAT
GPIO
GPIO Port G[1]
EECLK
GPIO
GPIO Port G[0]



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