EP9312 datasheet(14/62 Pages) CIRRUS

Il numero della parte	EP9312

Spiegazioni elettronici	Universal Platform System-on-chip Processor

PDF	62 Pages

Scroll/Zoom	100%

Produttore elettronici	CIRRUS [Cirrus Logic]

Homepage	http://www.cirrus.com

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14 / 62 page

DS515PP7

EP9312

Universal Platform SOC Processor

Timings

Timing Diagram Conventions

This data sheet contains one or more timing diagrams. The following key explains the components used in these

diagrams. Any variations are clearly labelled when they occur. Therefore, no additional meaning should be attached

unless specifically stated.

Figure 1. Timing Diagram Drawing Key

Timing Conditions

Unless specified otherwise, the following conditions are true for all timing measurements.

•TA = 0 to 70° C

• CVDD = VDD_PLL = 1.8V

•RVDD = 3.3 V

• All grounds = 0 V

• Logic 0 = 0 V, Logic 1 = 3.3 V

• Output loading = 50 pF

• Timing reference levels = 1.5 V

• The Processor Bus Clock (HCLK) is programmable and is set by the user. The frequency is typically between

33 MHz and 100 MHz (92 MHz for industrial conditions).

Clock

High to Low

High/Low to High

Bus Change

Bus Valid

Undefined/Invalid

Valid Bus to Tristate

Bus/Signal Omission

EP9312 Scheda tecnica(PDF) 14 Page - Cirrus Logic