EP9312 datasheet(30/62 Pages) CIRRUS

30 / 62 page

DS515PP7

EP9312

Universal Platform SOC Processor

IDE Interface

Note:

1. t0 is the minimum total cycle time, t2 is the minimum DIORn / DIOWn assertion time, and t2i is the minimum DIORn / DIOWn

negation time. A host implementation shall lengthen t2 and/or t2i to ensure that t0 is equal to or greater than the value

reported in the devices IDENTIFY DEVICE data. A device implementation shall support any legal host implementation.

2. This parameter specifies the time from the negation edge of DIORn to the time that the data bus is released by the device.

3. The delay from the activation of DIORn or DIOWn until the state of IORDY is first sampled. If IORDY is inactive then the host

shall wait until IORDY is active before the register transfer cycle is completed. If the device is not driving IORDY negated at

the tA after the activation of DIORn or DIOWn, then t5 shall be met and tRD is not applicable. If the device is driving IORDY

negated at the time tA after the activation of DIORn or DIOWn, then tRD shall be met and t5 is not applicable.

4. Timings based upon software control. See User’s Guide.

5. ATA / ATAPI standards prior to ATA / ATAPI-5 inadvertently specified an incorrect value for mode 2 time t0 by utilizing the

16-bit PIO value.

6. All IDE timing is based upon HCLK = 100 MHz.

Parameter

Symbol

Mode 0

(in ns)

Mode 1

(in ns)

Mode 2

(in ns)

Mode 3

(in ns)

Mode 4

(in ns)

Cycle time

(min)

(Notes 1, 4, 5)

600

383

330

180

120

Address valid to DIORn / DIOWn setup

(min)

(Note 4)

DIORn / DIOWn pulse width 8-bit

(min)

(Note 1, 4)

290

DIORn / DIOWn recovery time

(min)

(Note 1, 4)

t2i

DIOWn data setup

(min)

(Note 4)

DIOWn data hold

(min)

0000

DIORn data setup

(min)

DIORn data hold

(min)

0000

DIORn data high impedance state

(max)

(Note 2, 4)

t6z

DIORn / DIOWn to address valid hold

(min)

(Note 4)

Read Data Valid to IORDY

(min)

active (if IORDY initially low after tA)

(Note 4)

tRD

0000

IORDY Setup time

(Note 3, 4)

IORDY Pulse Width

(max)

(Note 4)

1250

IORDY assertion to release

(max)

5555

DIOWn assert to data valid

(max)

tDDV

EP9312 Scheda tecnica(PDF) 30 Page - Cirrus Logic

EP9312 Scheda tecnica(HTML) 30 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62

Scheda tecnica Scarica

Link URL