EP9312 datasheet(33/62 Pages) CIRRUS

33 / 62 page

DS515PP7

EP9312

Universal Platform SOC Processor

Note:

1. Device address consists of signals IDECS0n, IDECS1n and IDEDA (2:0)

2. Data consists of DD (15:0)

3. The negation of IORDY by the device is used to extend the register transfer cycle. The determination of whether the cycle is

to be extended is made by the host after tA from the assertion of DIORn or DIOWn. The assertion and negation or IORDY

are described in the following three cases:

3-1 Device never negates IORDY, devices keeps IORDY released: no wait is generated.

3-2 Device negates IORDY before tA, but causes IORDY to be asserted before tA. IORDY is released prior to negation

and may be asserted for no more than tC before release: no wait generated.

3-3 Device negates IORDY before tA. IORDY is released prior to negation and may be asserted for no more than tC

before release: wait generated. The cycle completes after IORDY is reasserted. For cycles where a wait is generated

and DIORn is asserted, the device shall place read data on DD (15:0) for tRD before asserting IORDY.

Figure 18. PIO Data Transfer to/from Device

ADDR valid

(Note 1)

DIORn/

DIOWn

WRITE

DD(15:0)

(Note 2)

READ

DD(15:0)

(Note 2)

IORDY

(Note 3,3-1)

IORDY

(Note 3,3-2)

IORDY

(Note 3,3-3)

DDV

EP9312 Scheda tecnica(PDF) 33 Page - Cirrus Logic