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EP9312 Scheda tecnica(PDF) 28 Page - Cirrus Logic |
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EP9312 Scheda tecnica(HTML) 28 Page - Cirrus Logic |
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28 / 62 page ![]() 28 ©Copyright 2005 Cirrus Logic (All Rights Reserved) DS515PP7 EP9312 Universal Platform SOC Processor Static Memory Single Write Wait Cycle Parameter Symbol Min Typ Max Unit WAIT to WRn deassert delay time tWRd tHCLK × 2 - tHCLK × 4 ns CSn assert to WAIT time tWAITd -- tHCLK × (WST1-2) ns WAIT assert time tWAITpw tHCLK × 2 - tHCLK × 510 ns WAIT to CSn deassert delay time tCSnd tHCLK × 3 - tHCLK × 5 ns Figure 15. Static Memory Single Write Wait Cycle Timing Measurement CSn WRn RDn DQMn AD DA WAIT t WAITpw t WAITd t CSnd t WRd |
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