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EP9312 Scheda tecnica(PDF) 26 Page - Cirrus Logic

Il numero della parte EP9312
Spiegazioni elettronici  Universal Platform System-on-chip Processor
PDF  62 Pages
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Produttore elettronici  CIRRUS [Cirrus Logic]
Homepage  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

EP9312 Scheda tecnica(HTML) 26 Page - Cirrus Logic

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©Copyright 2005 Cirrus Logic (All Rights Reserved)
DS515PP7
EP9312
Universal Platform SOC Processor
Static Memory Burst Write Cycle
Note:
These characteristics are valid when the Page Mode Enable (Burst Mode) bit is set. See the User's Guide for details.
Parameter
Symbol
Min
Typ
Max
Unit
AD setup to WRn assert time
tADs
tHCLK − 3
ns
AD hold from WRn deassert time
tADh
tHCLK × 2
ns
WRN/DQMn deassert to AD transition time
tADd
tHCLK + 6
ns
CSn hold from WRn deassert time
tCSh
7
ns
CSn to WRn assert delay time
tWRd
2ns
CSn to DQMn assert delay time
tDQMd
1ns
DQMn assert time
tDQpwL
tHCLK × (WST1 + 1)
ns
DQMn deassert time
tDQpwH
(tHCLK × 2) + 14
ns
WRn assert time
tWRpwL
tHCLK × (WST1 + 11)
ns
WRn deassert time
tWRpwH
(tHCLK × 2) + 7
ns
WRn/DQMn deassert to DA transition time
tDAh
tHCLK
ns
WRn/DQMn assert to DA valid time
tDAv
8ns
Figure 13. Static Memory Burst Write Cycle Timing Measurement
AD
CSn
WRn
RD
DQMn
DA
WAIT
t
ADs
t
ADd
t
WRpwL
t
DQpwL
t
DQpwH
t
WRpwH
t
DAv
t
DAh
t
WRd
t
DQMd
t
CSh
t
ADh



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