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EP9312 Scheda tecnica(PDF) 25 Page - Cirrus Logic

Il numero della parte EP9312
Spiegazioni elettronici  Universal Platform System-on-chip Processor
PDF  62 Pages
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Produttore elettronici  CIRRUS [Cirrus Logic]
Homepage  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

EP9312 Scheda tecnica(HTML) 25 Page - Cirrus Logic

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25
EP9312
Universal Platform SOC Processor
Static Memory Burst Read Cycle
Note:
These characteristics are valid when the Page Mode Enable (Burst Mode) bit is set. See the User's Guide for details.
Parameter
Symbol
Min
Typ
Max
Unit
CSn assert to Address 1 transition time
tADd1
-
tHCLK × (WST1 + 1)
-ns
Address assert time
tADd2
-
tHCLK × (WST2 + 1)
-ns
AD transition to CSn deassert time
tADd3
-
tHCLK × (WST1 + 2)
-ns
AD hold from CSn deassert time
tADh
tHCLK
--
ns
CSn to RDn delay time
tRDd
--
3
ns
CSn to DQMn assert delay time
tDQMd
--
1
ns
DA setup to AD transition time
tDAs1
15
-
-
ns
DA setup to CSn deassert time
tDAs2
tHCLK + 12
--
ns
DA hold from AD transition time
tDAh1
0-
-
ns
DA hold from RDn deassert time
tDAh2
0-
-
ns
Figure 12. Static Memory Burst Read Cycle Timing Measurement
AD
CSn
WRn
RDn
DQMn
DA
t
ADd1
t
ADd2
t
ADd2
t
RDd
t
DQMd
t
DAs1
t
DAh1
t
DAs1
t
DAh1
t
DAs1
t
DAh1
t
DAs2
t
DAh2
t
ADh
WAIT
t
ADd3
t
ADs



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