FS23 datasheet(25/230 Pages) NXP

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NXP Semiconductors

FS23

Safety system basis chip (SBC) with power management, CAN FD and LIN transceivers

12.5 INIT state machine

From any

Mx state

VBOS < VBOS_por

Or VDIG < VDIG_por

Or VDIG > VDIG_ov

VBOS > VBOS_por

And VDIG > VDIG_por

And VDIG < VDIG_ov

Go2INIT = 1

And Mode = NORMAL (M7)

Wake-up from LP mode (M2)

And LOAD_OTP_BYP = 0

Restart from Fail-Safe state

And LOAD_OTP_BYP = 0

Periodic CRC disabled

INIT registers unlocked

WD infinite period writing possible

LOCK_INIT set to 1

Periodic CRC enabled

INIT registers locked

WD infinite period writing locked

LOCK_INIT = 0

And WD_OK

INIT_1

INIT state

INIT_0

Power down

aaa-051438

Legend: BLUE: Device action, GREEN: Safety related device action, BLACK: Device state

Figure 12. Simplified INIT state diagram

At power-on reset, the device is automatically in INIT state. In this mode, the INIT registers (FS_I_xxxxx) are

available for writing and configure the device safety features and reactions. When the device enters INIT state,

LOCK_INIT bit is set to 1. The cyclic CRC check that protects these registers is disabled. Also in this mode,

the watchdog period can be configured as infinite, which is equivalent to disabling the watchdog. For an MCU

programming example, see Section 12.8.

To exit the INIT state, LOCK_INIT is cleared by writing 1, and then a good watchdog refresh must be sent.

The INIT registers, as well as the possibility to select infinite watchdog period configuration, are then protected

against write access. The cyclic CRC check on the INIT registers is activated, and occurs every 5 ms.

At power-on reset, the first good watchdog refresh must be sent in less than 256 ms, which is the default

watchdog period. If not, the watchdog error counter will be incremented, see Section 19.2.2.

In Normal mode, the INIT state can be accessed again by sending a GO2INIT request by SPI / I2C. In this case,

if the watchdog is enabled, it must be refreshed every watchdog period.

The device will also enter the INIT state when waking up from LPON or LPOFF states, or when restarting from

Fail-safe state, in case the OTP register loading is not bypassed. This allows the MCU to reconfigure the safety

features if needed.

Note: If the device goes into LPON, LPOFF, or Fail-safe mode while in INIT state, it stays in INIT state, which

can lead to misconfiguration of the device. Therefore, it is recommended to read the INIT_S status bit in

M_STATUS register before going to LPON or LPOFF mode, and to go only if the device is no longer in INIT

state.

FS23

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 7.0 — 16 October 2024

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