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NXP Semiconductors

FS23

Safety system basis chip (SBC) with power management, CAN FD and LIN transceivers

WD refresh OK

aaa-051467

WD Refresh NOT OK /

WD_OFF

WD refresh NOT OK /

WD_OFF / WD refresh OK

WD refresh NOT OK /

WD_OFF / WD refresh OK

WD refresh NOT OK /

WD_OFF / WD refresh OK

WD refresh OK

WD Refresh NOT OK /

WD_OFF

WD Refresh NOT OK /

WD_OFF

WD Refresh NOT OK /

WD_OFF

WD_RFR_LIMIT = 10

WD_RFR_LIMIT = 01

WD refresh NOT OK /

WD_OFF / WD refresh OK

WD refresh NOT OK /

WD_OFF

WD_RFR_LIMIT = 00

WD refresh NOT OK /

WD_OFF

WD refresh NOT OK /

WD_OFF

WD refresh OK

WD_RFR_LIMIT = 11

Figure 46. Watchdog refresh counter configurations

19.2.4 Watchdog error impact

When the watchdog error counter reaches its maximum value, in Normal mode or in LPON mode, the fail-safe

reaction on RSTB, FS0B, or LIMP0 is configurable with the WD_RSTB/FS0B/LIMP0_IMPACT bits during the

INIT phase. If it happens in LPON mode, the device also wakes up.

WD_RSTB/FS0B/LIMP0_IMPACT

WD impact on RSTB/FS0B/LIMP0

No effect on the pin

1 (default)

The pin RSTB/FS0B/LIMP0 is asserted

Reset condition

POR

Table 39. Watchdog error impact configuration

19.2.5 MCU fault recovery strategy

The fault recovery strategy feature is enabled by SPI/I2C using WDW_REC_EN bit. This function extends

the watchdog window to allow the MCU to perform a fault recovery strategy. The goal is to not reset the MCU

while it is trying to recover the application after a failure event. When a fault is triggered by the MCU via

its FCCU pins, the FS0B and LIMP0 pins are asserted by the device depending on the FCCU error impact

configuration. The RSTB pin is not asserted to keep the MCU availability and the watchdog window duration

becomes automatically an open window (no more duty cycle). This open window duration is configurable with

the WDW_RECOVERY[3:0] bits.

FS23

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 7.0 — 16 October 2024

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