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FS23 Scheda tecnica(PDF) 99 Page - NXP Semiconductors |
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FS23 Scheda tecnica(HTML) 99 Page - NXP Semiconductors |
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99 / 230 page ![]() NXP Semiconductors FS23 Safety system basis chip (SBC) with power management, CAN FD and LIN transceivers 20 MCU communication The FS23 provides both I2C and SPI interfaces with shared pins, for device configuration, control and diagnostic, in Normal and LPON modes. The choice of the interface is done by OTP. By default and when SPI_EN_OTP = 0, the I2C interface is selected. In this case, pins 27 and 28 are used respectively as SCL and SDA signals, and pins 25 and 26 are available as LVO6 and LVI5 digital I/Os. When SPI_EN_OTP = 1, the SPI interface is selected. In this case, pins 25 to 28 are used respectively as MISO, MOSI, SCK, and CSB pins. 20.1 I2C communication interface 20.1.1 I2C interface overview The FS23 I2C interface follows the Fast mode-plus definition up to 1 Mbit/s. High-speed mode (3.4 Mbit/s) is not supported by the device. I2C interface protocol requires a device address for addressing the target IC on a multidevice bus. The FS23 has one device address to access the logic. This I2C addresses is set by OTP (I2CDEVADDR_OTP). The I2C interface uses the VDDIO pin as power input and it is compatible with 3.3 V and 5.0 V input supply. Timing, diagrams, and further details can be found in the NXP I2C specification. Refer to UM10204 Rev. 7. An I2C message has the following arrangement: B39 B38 B37 B36 B35 B34 B33 B32 ID[6:0] R/W Device address R/W B31 B30 B29 B28 B27 B26 B25 B24 B23 B22 B21 B20 B19 B18 B17 B16 0 ADR[6:0] DATA[15:8] 0 Register address Data MSB B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 DATA[7:0] CRC[7:0] Data LSB CRC Table 62. I2C message construction Bit B32 must be set to 0 to execute a write command, and to 1 to execute a read command. A read command is composed of two I2C accesses: • The first access is the request with the device address and the register address. • The second access is the answer with the data contained in the register and the CRC. First access Second access Device address + R/W 0b0 + Register address Device address + R/W Data 8-bit CRC 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0x40 0x06 0x41 0x0009 0x5F Table 63. Read command example FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 7.0 — 16 October 2024 Document feedback 99 / 230 |
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