FS23 datasheet(27/230 Pages) NXP

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NXP Semiconductors

FS23

Safety system basis chip (SBC) with power management, CAN FD and LIN transceivers

aaa-051440

VBAT

Vsup > Vsup_UV

Power-up sequence

NORMAL mode

Tslot

VBOS

VDIG

Slot 0

(V1)

Slot 1

Slot 2

RSTB

Tslot

Trstb_dur

256 ms for INIT phase

Tslot

Figure 14. Power-up sequence example

12.7 Debug and OTP modes

OTP mode and Debug mode are intended for use during the development process, not in production

applications or vehicles. OTP mode is intended for OTP emulation and OTP programming.

OTP emulation and programming performed by the customer is allowed during engineering development using

NXP’s latest graphical user interface and socketed evaluation board. Customer is not allowed to perform OTP

programming for production purposes. Only NXP or a recommended third party are allowed to program the

device for production purposes.

The FS23 enters Debug mode in M3 state of the main state machine when VDBG (DBG pin voltage) >

VDBG_MODE. NXP recommend's connecting the DBG pin to the VBOS pin through a diode (VDBG = VBOS – Vd ≈

4.1 V). The Debug mode disables the watchdog (period configured as infinite), the RSTB 8 s timer, the Fail-Safe

mode entry via the fault error counter, and locks FS0B low. In Debug mode, CAN and LIN transceivers are set

in Active mode by default. The Debug mode status is reported by the DBG_MODE bit in M_SYS1_CFG. To exit

Debug mode, write 1 in the DBG_EXIT bit in the M_SYS1_CFG register.

FS23

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 7.0 — 16 October 2024

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FS23 Scheda tecnica(PDF) 27 Page - NXP Semiconductors