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FS23 Scheda tecnica(PDF) 84 Page - NXP Semiconductors

Il numero della parte FS23
Spiegazioni elettronici  Safety system basis chip (SBC) with power management, CAN FD and LIN transceivers
PDF  230 Pages
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Produttore elettronici  NXP [NXP Semiconductors]
Homepage  http://www.nxp.com
Logo NXP - NXP Semiconductors

FS23 Scheda tecnica(HTML) 84 Page - NXP Semiconductors

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NXP Semiconductors
FS23
Safety system basis chip (SBC) with power management, CAN FD and LIN transceivers
The polarity of the FCCU fault signals is configurable with FCCU12_FLT_POL bit during the INIT_FS phase.
FCCU12_FLT_POL
FCCU12 polarity
0 (default)
FCCU1 = 0 or FCCU2 = 1 level is a fault
1
FCCU1 = 1 or FCCU2 = 0 level is a fault
Reset condition
POR
Table 43. FCCU12 polarity configuration
When FCCU fault is detected in bi-stable protocol, the fail-safe reaction on RSTB, FS0B, or LIMP0 pins is
configurable with the FCCU1_RSTB/FS0B/LIMP0_IMPACT bits during the INIT phase.
FCCU1_RSTB/FS0B/LIMP0_IMPACT
FCCU12 impact on RSTB/FS0B/LIMP0
0
No effect on the pin
1 (default)
The pin RSTB/FS0B/LIMP0 is asserted
Reset condition
POR
Table 44. FCCU12 error impact configuration
19.3.2 FCCU1, FCCU2 independent monitoring
When FCCU1 and/or FCCU2 are used independently, the FCCU inputs can monitor two different and
independent error signals. These error signals can be either steady-state level signals or PWM signals.
When the error signal(s) is/are steady-state level signal(s), the polarity of each FCCU fault signal is configurable
with FCCUx_FLT_POL bits during the INIT phase.
FCCU1_FLT_POL
FCCU1 polarity
0 (default)
FCCU1 low level is a fault
1
FCCU1 high level is a fault
Reset condition
POR
FCCU2_FLT_POL
FCCU2 polarity
0 (default)
FCCU2 low level is a fault
1
FCCU2 high level is a fault
Reset condition
POR
Table 45. FCCUx polarity configuration
When the error signal(s) is/are PWM signal(s), the error state is reported when the high-level signal duration is <
FCCU12HFDET or when the low-level signal duration is > FCCU12LFDET
The fail-safe reaction on RSTB, FS0B, or LIMP0 to an FCCU fault detection is configurable with the
FCCUx_RSTB/FS0B/LIMP0_IMPACT bits during the INIT phase.
FCCU1_RSTB/FS0B/LIMP0_IMPACT
FCCU1 impact on RSTB/FS0B/LIMP0
0
No effect on the pin
1 (default)
The pin RSTB/FS0B/LIMP0 is asserted
Reset condition
POR
FCCU2_RSTB/FS0B/LIMP0_IMPACT
FCCU2 impact on RSTB/FS0B/LIMP0
Table 46. FCCUx error impact configuration
FS23
All information provided in this document is subject to legal disclaimers.
© 2024 NXP B.V. All rights reserved.
Product data sheet
Rev. 7.0 — 16 October 2024
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