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FS23 Scheda tecnica(PDF) 26 Page - NXP Semiconductors |
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FS23 Scheda tecnica(HTML) 26 Page - NXP Semiconductors |
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26 / 230 page ![]() NXP Semiconductors FS23 Safety system basis chip (SBC) with power management, CAN FD and LIN transceivers 12.6 Power sequencing V1 is the first regulator to start automatically in Slot 0, then the other regulators start following the OTP power sequencing configuration. Three slots are available, from SLOT_0 to SLOT_2, to program the start-up sequence of V2 and V3 regulators, as well as I/Os release or assertion. The power-up sequence starts at SLOT_0 towards SLOT_2. The power-down sequence is executed in reverse order, starting at SLOT_2 toward SLOT_0. All regulators not assigned in any slot are not started during the power-up sequence. These regulators can be started (or not) later when the main state machine is in NORMAL mode with an SPI/I2C command to write in M_REG_CTRL register if they were enabled by OTP. Slot 0 duration depends on the device version. In the HVBUCK version (FS232x), Slot 0 lasts at least 500 µs and until the soft start of the DC-DC is done, which depends on the OTP configuration. In the HVLDO1 version (FS230x), it lasts 500 µs (fixed duration). Slot 1 and Slot 2 always last 500 µs. When waking up from LPON, it is possible to reduce the start-up time by bypassing Slot 1 and Slot 2. In this case, the V2 and V3 regulators must be configured to start in Slot 0, or later by SPI/I2C, as their correct soft start will not be guaranteed otherwise. Bypassing Slot 1 and Slot 2 is enabled by SPI/I2C with SLOT_BYP bit. It can also be preconfigured by OTP using SLOT_BYP_OTP bit. aaa-051439 Power up Power down From WAIT VSUP To NORMAL SLOT_0 VSUP > VSUP_UV TSOFT_START_V1 and (TSLOT_UP or (SLOT_BYP = 1 and Go2LPON_latch = 1)) TSLOT_UP TSLOT_UP SLOT_BYP = 1 and Go2LPON_latch = 1 SLOT_1 SLOT_2 From NORMAL To LPON To LPOFF SLOT_2 Go2LPON = 1 or Go2LPOFF = 1 TSLOT_DOWN TSLOT_DOWN 10 µs TRAMP_DOWN_V1 + 10 µs SLOT_1 SLOT_0 Figure 13. Power sequencing FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 7.0 — 16 October 2024 Document feedback 26 / 230 |
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