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Motore di ricerca datesheet componenti elettronici |
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Motore di ricerca datesheet componenti elettronici |
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LMKDB1108FS Scheda tecnica(PDF) 23 Page - Texas Instruments |
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LMKDB1108FS Scheda tecnica(HTML) 23 Page - Texas Instruments |
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23 / 126 page  6.5 Electrical Characteristics (continued) over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tR, tF Rise/fall time on single-ended waveform, 20% to 80% Output swing programmed to 800 mV. Fastest slew rate. f0 = 156.25 MHz or 312.5 MHz 402 ps Output swing programmed to 900 mV. Fastest slew rate. f0 = 156.25 MHz or 312.5 MHz 419 ps DCD Duty cycle distortion Input duty cycle = 50% –1 1 % FREQUENCY AND TIMING CHARACTERISTICS f0 Operating frequency Automatic Output Disable functionality is disabled 1 400 MHz Automatic Output Disable functionality is enabled 25 400 MHz tstartup Startup time Cold start. Measured from VDD valid (90% of final VDD) to output clock stable(3). Input clock is provided before VDD is valid. PWRGD_PWRDN# pin is tied to VDD. f0 ≥ 100 MHz 0.4 ms Cold start. Measured from VDD valid (90% of final VDD) to output clock stable(3). Input clock is provided before VDD is valid. PWRGD_PWRDN# pin is tied to VDD. f0 < 100 MHz 0.8 ms tstable Clock stabilization time VDD is stable. Measured from PWRGD assertion(4) to output clock stable. f0 ≥ 100 MHz(3) 0.4 ms VDD is stable. Measured from PWRGD assertion(4) to output clock stable. f0 < 100 MHz(3) 0.8 ms tPD# Powerdown deassertion time Measured from PWRDN# deassertion(4) to output clock stable. f0 ≥ 100 MHz(3) 0.15 ms Measured from PWRDN# deassertion(4) to output clock stable. f0 < 100 MHz(3) 0.5 ms tOE Output enable/disable time Time elapsed from OE assertion/ deassertion(4) to output clock starts/stops 4 10 clk tLOS-assert LOS# assertion time Time elapsed from loss of input clock to LOS# assertion. f0 < 100 MHz 120 ns Time elapsed from loss of input clock to LOS# assertion. f0 ≥ 100 MHz 120 ns tLOS- deassert LOS# deassertion time Time elapsed from presence of input clock to LOS# deassertion. f0 < 100 MHz 340 ns Time elapsed from presence of input clock to LOS# deassertion. f0 ≥ 100 MHz 105 ns tAOD Automatic output disable time Time elapsed from LOS# assertion to output disable (both outputs are low/ low). f0 < 100 MHz 0.07 ns Time elapsed from LOS# assertion to output disable (both outputs are low/low), f0 ≥ 100 MHz 0.07 ns tAOE Automatic output enable time Time elapsed from LOS# deassertion to output clock stable. f0 < 100 MHz(3) 115 ns Time elapsed from LOS# deassertion to output clock stable, f0 ≥ 100 MHz(3) 22 ns tswitch Switch time Switch between two 100MHz input clocks (MUX only) 70 ns www.ti.com LMKDB1102, LMKDB1104, LMKDB1104FS LMKDB1108, LMKDB1108FS, LMKDB1112, LMKDB1120, LMKDB1120FS SNAS855F – NOVEMBER 2023 – REVISED NOVEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: LMKDB1102 LMKDB1104 LMKDB1104FS LMKDB1108 LMKDB1108FS LMKDB1112 LMKDB1120 LMKDB1120FS |
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