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LMKDB1108FS Scheda tecnica(PDF) 51 Page - Texas Instruments

Il numero della parte LMKDB1108FS
Spiegazioni elettronici  LMKDB11xx PCIe Gen 1 to Gen 7 Ultra Low Jitter LP-HCSL Clock Buffer Family
PDF  126 Pages
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LMKDB1108FS Scheda tecnica(HTML) 51 Page - Texas Instruments

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Table 9-21. R35 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
3
SBI_CLK_19
R
1h
Readback of Side-Band Disable for CLK19
2
SBI_CLK_18
R
1h
Readback of Side-Band Disable for CLK18
1
SBI_CLK_17
R
1h
Readback of Side-Band Disable for CLK17
0
SBI_CLK_16
R
1h
Readback of Side-Band Disable for CLK16
9.1.20 R38 Register (Offset = 26h) [Reset = 00h]
R38 is shown in Table 9-22.
Return to the Summary Table.
Table 9-22. R38 Register Field Descriptions
Bit
Field
Type
Reset
Description
7:1
RESERVED
R
0h
Reserved
0
WRITE_LOCK
W1C
0h
Non-clearable SMBus Write Lock bit. When written to one, the
SMBus control registers cannot be written to. This bit can only be
cleared by recycling power.
0h = SMBus Not locked for Writing
1h = SMBus Locked for Writing
9.1.21 R39 Register (Offset = 27h) [Reset = 00h]
R39 is shown in Table 9-23.
Return to the Summary Table.
Table 9-23. R39 Register Field Descriptions
Bit
Field
Type
Reset
Description
7:2
RESERVED
R
0h
Reserved
1
LOS_EVT
R/WSC
0h
LOS Event Status When high, indicates that a LOS event is
detected. Can be cleared by writing a 1 to the bit.
0h = LOS Event Not-Detected
1h = LOS Event Detected
0
WRITE_LOCK_RW1C
R/W
0h
Clearable SMBus Write Lock bit. When written to one, the SMBus
control registers cannot be written to. This bit can be cleared by
writing a 1 to the bit.
0h = SMBus Not Locked for Writing
1h = SMBus locked for writing
9.1.22 R91 Register (Offset = 5Bh) [Reset = 00h]
R91 is shown in Table 9-24.
Return to the Summary Table.
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LMKDB1102, LMKDB1104, LMKDB1104FS
LMKDB1108, LMKDB1108FS, LMKDB1112, LMKDB1120, LMKDB1120FS
SNAS855F – NOVEMBER 2023 – REVISED NOVEMBER 2025
Copyright © 2025 Texas Instruments Incorporated
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