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LMKDB1108FS Scheda tecnica(PDF) 84 Page - Texas Instruments

Il numero della parte LMKDB1108FS
Spiegazioni elettronici  LMKDB11xx PCIe Gen 1 to Gen 7 Ultra Low Jitter LP-HCSL Clock Buffer Family
PDF  126 Pages
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Produttore elettronici  TI2 [Texas Instruments]
Homepage  https://www.ti.com
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LMKDB1108FS Scheda tecnica(HTML) 84 Page - Texas Instruments

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Table 9-99. R92 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
3:0
SLEWRATE_OPT_3
R/W
6h/Ah
There are four register assignments each storing a slew rate value
(chosen out of the 16 available slew rate values). This register bits
relate to the 3rd option. Go to Programmable Output Slew Rate
section for more information.
0h = 0 (fastest)
1h = 1
2h = 2
3h = 3
4h = 4
5h = 5
6h = 6 (Default for LMKDB1104FS)
7h = 7
8h = 8
9h = 9
Ah = 10 (Default for LMKDB1104)
Bh = 11
Ch = 12
Dh = 13
Eh = 14
Fh = 15 (slowest)
9.4.21 R98 Register (Offset = 62h) [Reset = 00h]
R98 is shown in Table 9-100.
Return to the Summary Table.
Table 9-100. R98 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
SLEWRATE_SEL_CLK1_
LSB
R/W
0h
LSB CLK1 Slew Rate Control
6:5
RESERVED
R
0h
Reserved
4
SLEWRATE_SEL_CLK0_
LSB
R/W
0h
LSB CLK0 Slew Rate Control
3:0
RESERVED
R
0h
Reserved
9.4.22 R99 Register (Offset = 63h) [Reset = 00h]
R99 is shown in Table 9-101.
Return to the Summary Table.
Table 9-101. R99 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
RESERVED
R
0h
Reserved
6
SLEWRATE_SEL_CLK3_
LSB
R/W
0h
LSB CLK3 Slew Rate Control
5:3
RESERVED
R
0h
Reserved
2
SLEWRATE_SEL_CLK2_
LSB
R/W
0h
LSB CLK2 Slew Rate Control
1:0
RESERVED
R
0h
Reserved
LMKDB1102, LMKDB1104, LMKDB1104FS
LMKDB1108, LMKDB1108FS, LMKDB1112, LMKDB1120, LMKDB1120FS
SNAS855F – NOVEMBER 2023 – REVISED NOVEMBER 2025
www.ti.com
84
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Product Folder Links: LMKDB1102 LMKDB1104 LMKDB1104FS LMKDB1108 LMKDB1108FS LMKDB1112 LMKDB1120 LMKDB1120FS



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