LMKDB1108FS datasheet(33/126 Pages) TI2

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8 Detailed Description

8.1 Overview

LMKDB11xx are DB2000QL compliant clock buffers that distribute LP-HCSL clocks designed for PCIe Gen

1 through 7 applications with ultra-low additive jitter and ultra-low propagation delay. The LMKDB11xx buffer

devices allow for enough jitter margin for the entire clock path mainly required for PCIe Gen 5, Gen 6 and Gen

7 buffer cascading and Ethernet fan-out applications. The LMKDB11xx also support both 1.8V and 3.3V supply

voltages for better design flexibility.

LMKDB11xx have individual OE controls for all outputs, which provides more design flexibility. Each output of

each device also has programmable slew rate, programmable output amplitude swing, and automatic output

disable. The devices support 100Ω or 85Ω LP-HCSL and fail-safe inputs and outputs denoted by the part

number as shown in Section 4, with output frequencies of up to 400MHz.

LMKDB11xx have pin mode, SMBus mode, and Side Band Interface (SBI) mode, which can all be used at the

same time. Refer to Section 5 for more details one each option available on specific device. SBI enables or

disables output clocks at a much faster speeds (up to 25MHz) as compared to SMBus. Furthermore, because

both SBI and SMBus can operate at the same time, SMBus can still be used to take over device control and

readback status after power-up. For more details please refer to Section 8.4

Refer to Section 8 for the detailed descriptions of the devices pins and the Register Map for more details on the

device registers.

8.2 Functional Block Diagram

1. LMKDB1116/13/12/8/4 only. Other devices support SMBus.

2. Some devices mux SBI with OE# pins. Refer to specific device pinouts.

3. This diagram doesn’t apply to LMKDB1102.

CLK0_P

CLK0_N

CLK[N-1]_P

LOS#

Input

Detection

Digital Control

(Side Band Interface,

SMBus,

Glitchless Output

Enable/Disable)

SMB_DATA

SMB_CLK

CLK[N-1]_N

SBI_OUT

CLKIN_P

CLKIN_N

OE[N-1]:0]#

SBI_EN

SBI_IN

SBI_CLK

SHFT_LD#

SADR[1:0]_tri

PWRGD/PWRDN#

SLEWRATE_SEL

N = Number of output channels

Note 2

Note 1

Note 2

Figure 8-1. LMKDB11xx Functional Block Diagram

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LMKDB1102, LMKDB1104, LMKDB1104FS

LMKDB1108, LMKDB1108FS, LMKDB1112, LMKDB1120, LMKDB1120FS

SNAS855F – NOVEMBER 2023 – REVISED NOVEMBER 2025

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