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Motore di ricerca datesheet componenti elettronici |
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Motore di ricerca datesheet componenti elettronici |
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LMKDB1108FS Scheda tecnica(PDF) 29 Page - Texas Instruments |
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LMKDB1108FS Scheda tecnica(HTML) 29 Page - Texas Instruments |
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29 / 126 page  6.5 Electrical Characteristics (continued) over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT I/O CHARACTERISTICS VIH Input voltage high 2-level logic input, VDD = 3.3 V ± 10% 2 VDD + 0.3 V VIL Input voltage low –0.3 0.8 V VIH Input voltage high 3-level logic input, VDD = 3.3 V ± 10% 2.4 VDD + 0.3 V VIM Input voltage mid 1.2 1.8 V VIL Input voltage low –0.3 0.8 V VIH Input voltage high 2-level logic input, VDD = 1.8 V ± 5% 1.3 VDD + 0.3 V VIL Input voltage low –0.3 0.4 V VIH Input voltage high 3-level logic input, VDD = 1.8 V ± 5% 1.3 VDD + 0.3 V VIM Input voltage mid 0.65 0.95 V VIL Input voltage low –0.3 0.4 V VOH Output high voltage SBI_OUT, IOH = -2 mA 2.4 VDD + 0.3 V VOL Output low voltage SBI_OUT, IOL = 2 mA 0.4 V Ileakage Output leakage current (LMKDB1120FS, LMKDB1108FS, LMKDB1104FS) Output leakage current when outputs are connected to VDD ± 10% while device is unpowered. 10 µA IIN Input leakage current CLKINx_P –40 40 µA CLKINx_N –40 40 µA single-ended inputs with internal pulldown –30 30 µA single-ended inputs without internal pulldown –5 5 µA 3-level logic input –30 30 µA RPU,PD Internal pullup/pulldown resistor for single-ended inputs 120 kΩ SMBUS ELECTRICAL CHARACTERISTICS VIH SMB_CLK, SMB_DATA input high voltage 0.8 × VDD V VIL SMB_CLK, SMB_DATA input low voltage 0.3 × VDD V VHYS Hysteresis of Schmitt Trigger Inputs 0.05 × VDD V VOL SMB_DATA output low voltage IOL = 4 mA 0.4 V ILEAK SMB_CLK, SMB_DATA input leakage –10 10 µA CPIN SMB_CLK, SMB_DATA pin capacitance 10 pF (1) PCIe AC test load (2) DB2000QL DC test load (3) First clock edge is used for timing measurements. Clock outputs are muted until stabilized. (4) For input pins, assertion or deassertion starts when the input voltage reaches the minimum voltage required for a "high" level, or the maximum voltage required for a "low" level (5) All power supply pins are tied together. A 0.1µF capacitor is placed close to each power supply pin. 50 mVpp ripple is applied before the decoupling capacitors. Measure the spur level at the clock output (6) DB2000QL AC test load (7) Slew rate is highly dependent on PCB trace characteristics www.ti.com LMKDB1102, LMKDB1104, LMKDB1104FS LMKDB1108, LMKDB1108FS, LMKDB1112, LMKDB1120, LMKDB1120FS SNAS855F – NOVEMBER 2023 – REVISED NOVEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 29 Product Folder Links: LMKDB1102 LMKDB1104 LMKDB1104FS LMKDB1108 LMKDB1108FS LMKDB1112 LMKDB1120 LMKDB1120FS |
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