LMKDB1108FS datasheet(34/126 Pages) TI2

34 / 126 page

CLK1_P

CLK1_N

CLK2_P

LOS#

Input

Detection

Digital Control

(Glitchless Output Active/

Inactive control, Output

Impedance control)

CLK2_N

CLKIN_P

CLKIN_N

OE1#

OE2#

ZOUT_SEL

Figure 8-2. LMKDB1102 Functional Block Diagram

8.3 Feature Description

8.3.1 Input Features

8.3.1.1 Running Input Clocks When Device is Powered Off

The device supports running input clocks when power is off. This is different than the fail-safe feature where the

input can be pulled to static VDD when device power is off. This is useful if clock inputs are available before

power is provided to the clock buffer.

8.3.1.2 Fail-Safe Inputs

All clock input pins and digital input pins support fail-safe. Fail-safe means a pin can be driven to VDD when

device power is off, without causing any leakage or reliability problem. For example, an OE# pin can be driven

to VDD before device power is up so that the output stays muted until the OE# pin goes low, sometime after

power-up.

8.3.1.3 Input Configurations

LMKDB11xx devices input buffer stage supports four different configurations:

• DC coupled HCSL inputs.

• DC coupled LVDS input signal with external 100Ω termination resistor.

• AC coupled inputs with internal self-bias. See AC-Coupled or DC-Coupled Clock Inputs for more details.

• Internal 50Ω to ground terminations. See Internal Termination for Clock Inputs for more details.

All the devices with two inputs have individual AC coupling and input termination option. To configure each input,

refer to register map for configuration bits.

LMKDB1102, LMKDB1104, LMKDB1104FS

LMKDB1108, LMKDB1108FS, LMKDB1112, LMKDB1120, LMKDB1120FS

SNAS855F – NOVEMBER 2023 – REVISED NOVEMBER 2025

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