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Motore di ricerca datesheet componenti elettronici |
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Motore di ricerca datesheet componenti elettronici |
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LMKDB1108FS Scheda tecnica(PDF) 64 Page - Texas Instruments |
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LMKDB1108FS Scheda tecnica(HTML) 64 Page - Texas Instruments |
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64 / 126 page  Table 9-50. R92 Register Field Descriptions (continued) Bit Field Type Reset Description 3:0 SLEWRATE_OPT_3 R/W Ah There are four register assignments each storing a slew rate value (chosen out of the 16 available slew rate values). This register bits relate to the 3rd option. Go to Programmable Output Slew Rate section for more information. 0h = 0 1h = 1 2h = 2 3h = 3 4h = 4 5h = 5 6h = 6 7h = 7 8h = 8 9h = 9 Ah = 10 Bh = 11 Ch = 12 Dh = 13 Eh = 14 Fh = 15 9.2.21 R97 Register (Offset = 61h) [Reset = 12h] R97 is shown in Table 9-51. Return to the Summary Table. Table 9-51. R97 Register Field Descriptions Bit Field Type Reset Description 7 SLEWRATE_CTRL_MOD _E R/W 0h Sets which mode is used to change the outputs slew rates 0h = Pin mode 1h = SMBus mode 6 RESERVED R 0h Reserved 5:3 RESERVED R 0h Reserved 2:0 RESERVED R 0h Reserved 9.2.22 R98 Register (Offset = 62h) [Reset = 00h] R98 is shown in Table 9-52. Return to the Summary Table. Table 9-52. R98 Register Field Descriptions Bit Field Type Reset Description 7 SLEWRATE_SEL_CLK5_ _LSB R/W 0h LSB CLK5 Slew Rate Control 6 RESERVED R 0h Reserved 5 SLEWRATE_SEL_CLK4_ _LSB R/W 0h LSB CLK4 Slew Rate Control 4 SLEWRATE_SEL_CLK3_ _LSB R/W 0h LSB CLK3 Slew Rate Control 3 RESERVED R 0h Reserved 2 SLEWRATE_SEL_CLK2_ _LSB R/W 0h LSB CLK2 Slew Rate Control 1 SLEWRATE_SEL_CLK1_ _LSB R/W 0h LSB CLK1 Slew Rate Control LMKDB1102, LMKDB1104, LMKDB1104FS LMKDB1108, LMKDB1108FS, LMKDB1112, LMKDB1120, LMKDB1120FS SNAS855F – NOVEMBER 2023 – REVISED NOVEMBER 2025 www.ti.com 64 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated Product Folder Links: LMKDB1102 LMKDB1104 LMKDB1104FS LMKDB1108 LMKDB1108FS LMKDB1112 LMKDB1120 LMKDB1120FS |
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