H8SSLASH2214 datasheet(33/936 Pages) RENESAS

33 / 936 page

Rev.4.00 Sep. 18, 2008 Page xxxiii of lx

REJ09B0189-0400

4.4

Interrupts .............................................................................................................................. 87

4.5

Trap Instruction.................................................................................................................... 88

4.6

Stack Status after Exception Handling................................................................................. 89

4.7

Notes on Use of the Stack .................................................................................................... 90

Section 5 Interrupt Controller ............................................................................. 91

5.1

Overview.............................................................................................................................. 91

5.1.1

Features ................................................................................................................... 91

5.1.2

Block Diagram ........................................................................................................ 92

5.1.3

Pin Configuration.................................................................................................... 93

5.1.4

5.2

Register Descriptions ...........................................................................................................94

5.2.1

System Control Register (SYSCR) ......................................................................... 94

5.2.2

Interrupt Priority Registers A to D, F, G, J, K, M

(IPRA to IPRD, IPRF, IPRG, IPRJ, IPRK, IPRM)................................................. 95

5.2.3

IRQ Enable Register (IER) ..................................................................................... 96

5.2.4

IRQ Sense Control Registers H and L (ISCRH, ISCRL)........................................ 97

5.2.5

IRQ Status Register (ISR)....................................................................................... 98

5.3

Interrupt Sources .................................................................................................................. 99

5.3.1

External Interrupts .................................................................................................. 99

5.3.2

Internal Interrupts.................................................................................................. 101

5.3.3

Interrupt Exception Handling Vector Table.......................................................... 101

5.4

Interrupt Operation............................................................................................................. 104

5.4.1

Interrupt Control Modes and Interrupt Operation ................................................. 104

5.4.2

Interrupt Control Mode 0 ...................................................................................... 107

5.4.3

Interrupt Control Mode 2 ...................................................................................... 109

5.4.4

Interrupt Exception Handling Sequence ............................................................... 111

5.4.5

Interrupt Response Times ..................................................................................... 112

5.5

Usage Notes ....................................................................................................................... 113

5.5.1

Contention between Interrupt Generation and Disabling...................................... 113

5.5.2

Instructions that Disable Interrupts ....................................................................... 114

5.5.3

Times when Interrupts Are Disabled .................................................................... 114

5.5.4

Interrupts during Execution of EEPMOV Instruction........................................... 115

5.5.5

IRQ Interrupts ....................................................................................................... 115

5.5.6

NMI Interrupt Usage Notes................................................................................... 115

5.6

DTC and DMAC Activation by Interrupt .......................................................................... 116

5.6.1

Overview............................................................................................................... 116

5.6.2

Block Diagram ...................................................................................................... 116

5.6.3

Operation .............................................................................................................. 117

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