H8SSLASH2214 datasheet(47/936 Pages) RENESAS

47 / 936 page

Rev.4.00 Sep. 18, 2008 Page xlvii of lx

REJ09B0189-0400

Figure 6.23 On-Chip ROM Valid Extended Mode (Mode 6) Address Map............................... 172

Section 7 DMA Controller

Figure 7.1

Block Diagram of DMAC ....................................................................................... 174

Figure 7.2

Areas for Register Re-Setting by DTC (Example: Channel 0A)............................. 204

Figure 7.3

Operation in Sequential Mode................................................................................. 212

Figure 7.4

Example of Sequential Mode Setting Procedure ..................................................... 213

Figure 7.5

Operation in Idle Mode ........................................................................................... 215

Figure 7.6

Example of Idle Mode Setting Procedure................................................................ 216

Figure 7.7

Operation in Repeat mode ....................................................................................... 219

Figure 7.8

Example of Repeat Mode Setting Procedure........................................................... 220

Figure 7.9

Operation in Normal Mode ..................................................................................... 222

Figure 7.10 Example of Normal Mode Setting Procedure.......................................................... 223

Figure 7.11 Operation in Block Transfer Mode (BLKDIR = 0) ................................................. 225

Figure 7.12 Operation in Block Transfer Mode (BLKDIR = 1) ................................................. 226

Figure 7.13 Operation Flow in Block Transfer Mode ................................................................ 228

Figure 7.14 Example of Block Transfer Mode Setting Procedure.............................................. 229

Figure 7.15 Example of DMA Transfer Bus Timing.................................................................. 232

Figure 7.16 Example of Short Address Mode Transfer .............................................................. 233

Figure 7.17 Example of Full Address Mode (Cycle Steal) Transfer .......................................... 234

Figure 7.18 Example of Full Address Mode (Burst Mode) Transfer.......................................... 235

Figure 7.19 Example of Full Address Mode (Block Transfer Mode) Transfer .......................... 236

Figure 7.20 Example of

DREQ Pin Falling Edge Activated Normal Mode Transfer................. 237

Figure 7.21 Example of

DREQ Pin Falling Edge Activated Block Transfer Mode Transfer..... 238

Figure 7.22 Example of

DREQ Level Activated Normal Mode Transfer .................................. 239

Figure 7.23 Example of

DREQ Level Activated Block Transfer Mode Transfer ...................... 240

Figure 7.24 Example of Multi-Channel Transfer ....................................................................... 241

Figure 7.25 Example of Procedure for Continuing Transfer on Channel Interrupted

by NMI Interrupt ..................................................................................................... 243

Figure 7.26 Example of Procedure for Forcibly Terminating DMAC Operation....................... 244

Figure 7.27 Example of Procedure for Clearing Full Address Mode ......................................... 245

Figure 7.28 Block Diagram of Transfer End/Transfer Break Interrupt ...................................... 246

Figure 7.29 DMAC Register Update Timing ............................................................................. 247

Figure 7.30 Contention between DMAC Register Update and CPU Read................................. 248

Section 8 Data Transfer Controller (DTC)

Figure 8.1

Block Diagram of DTC ........................................................................................... 252

Figure 8.2

Flowchart of DTC Operation................................................................................... 262

Figure 8.3

Block Diagram of DTC Activation Source Control ................................................ 265

Figure 8.4

Correspondence between DTC Vector Address and Register Information ............. 268

Figure 8.5

Location of Register Information in Address Space................................................ 268

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