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H8S/2214 Scheda tecnica(PDF) 15 Page - Renesas Technology Corp |
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H8S/2214 Scheda tecnica(HTML) 15 Page - Renesas Technology Corp |
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15 / 936 page ![]() Rev.4.00 Sep. 18, 2008 Page xv of lx REJ09B0189-0400 Item Page Revisions (See Manual for Details) 10.7 Usage Notes (1) Module Stop Mode Settings 427 Description added Figure 10.53 Contention between TCNT Write and Overflow 436 Figure amended Write signal Address φ TCNT address TCNT TCNT write cycle T1 T2 H'FFFF M TCNT write data TCFV flag Prohibited 11.5.5 OVF Flag Clear Operation in Interval Timer Mode 451 Newly added 12.2.7 Serial Status Register (SSR) Bit 7—Transmit Data Register Empty (TDRE) 468 Note added Bit 7 TDRE Description 0 [Clearing conditions] • When 0 is written to TDRE after reading TDRE = 1 • When the DMAC or DTC* is activated by a TXI interrupt and writes data to TDR Note: * This bit is cleared by DTC when DISEL = 0 and furthermore the transfer counter is not 0. Bit 6—Receive Data Register Full (RDRF) Note added Bit 6 RDRF Description 0 [Clearing conditions] (Initial value) • When 0 is written to RDRF after reading RDRF = 1 • When the DMAC or DTC* is activated by an RXI interrupt and reads data from RDR Note: * This bit is cleared by DTC when DISEL = 0 and furthermore the transfer counter is not 0. |
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