H8SSLASH2214 datasheet(58/936 Pages) RENESAS

58 / 936 page

Rev.4.00 Sep. 18, 2008 Page lviii of lx

REJ09B0189-0400

Table 10.12 Interrupt Sources and DMA Controller (DMAC) and Data Transfer (DTC)

Activation................................................................................................................ 416

Section 11 Watchdog Timer (WDT)

Table 11.1

WDT Registers........................................................................................................ 439

Section 12 Serial Communication Interface (SCI)

Table 12.1

SCI Pins................................................................................................................... 457

Table 12.2

SCI Registers........................................................................................................... 458

Table 12.3

BRR Settings for Various Bit Rates (Asynchronous Mode) ................................... 473

Table 12.4

BRR Settings for Various Bit Rates (Clocked Synchronous Mode) ....................... 476

Table 12.5

Maximum Bit Rate for Each Frequency (Asynchronous Mode, when ABCS = 0). 478

Table 12.6

Maximum Bit Rate with External Clock Input

(Asynchronous Mode, when ABCS = 0)................................................................ 479

Table 12.7

Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode)....... 479

Table 12.8

SMR Settings and Serial Transfer Format Selection............................................... 488

Table 12.9

SMR and SCR Settings and SCI Clock Source Selection ....................................... 488

Table 12.10 SMR0, SCR0, SEMR0 Settings and SCI Clock Source Selection (SCI0 Only) ..... 489

Table 12.11 Serial Transfer Formats (Asynchronous Mode) ...................................................... 491

Table 12.12 Receive Errors and Conditions for Occurrence....................................................... 500

Table 12.13 SCI Interrupt Sources .............................................................................................. 519

Table 12.14 State of SSR Status Flags and Transfer of Receive Data ....................................... 521

Section 13 D/A Converter

Table 13.1

Pin Configuration .................................................................................................... 533

Table 13.2

D/A Converter Registers ......................................................................................... 533

Section 14 RAM

Table 14.1

RAM Register ......................................................................................................... 540

Section 15 ROM

Table 15.1

ROM Register ......................................................................................................... 544

Table 15.2

Operating Modes and ROM Area (F-ZTAT Version and Masked ROM Version) 545

Table 15.3

Differences between Boot Mode and User Program Mode..................................... 552

Table 15.4

Pin Configuration .................................................................................................... 554

Table 15.5

Table 15.6

Flash Memory Erase Blocks.................................................................................... 561

Table 15.7

Flash Memory Area Divisions ................................................................................ 562

Table 15.8

Setting On-Board Programming Modes.................................................................. 564

Table 15.9

System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate Is

Possible ................................................................................................................... 567

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