H8SSLASH2214 datasheet(83/936 Pages) RENESAS

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Section 2 CPU

Rev.4.00 Sep. 18, 2008 Page 23 of 872

REJ09B0189-0400

(d) Exception Vector Table and Memory Indirect Branch Addresses

In advanced mode the top area starting at H'00000000 is allocated to the exception vector table in

units of 32 bits. In each 32 bits, the upper 8 bits are ignored and a branch address is stored in the

lower 24 bits (figure 2.4). For details of the exception vector table, see section 4, Exception

Handling.

H'00000000

H'00000003

H'00000004

H'0000000B

H'0000000C

Exception vector table

Reserved

Power-on reset exception vector

(Reserved for system use)

Reserved

Exception vector 1

Reserved

Manual reset exception vector

H'00000010

H'00000008

H'00000007

Figure 2.4 Exception Vector Table (Advanced Mode)

The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses

an 8-bit absolute address included in the instruction code to specify a memory operand that

contains a branch address. In advanced mode the operand is a 32-bit longword operand, providing

a 32-bit branch address. The upper 8 bits of these 32 bits are a reserved area that is regarded as

H'00. Branch addresses can be stored in the area from H'00000000 to H'000000FF. Note that the

first part of this range is also the exception vector table.

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