H8SSLASH2214 datasheet(17/936 Pages) RENESAS

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Rev.4.00 Sep. 18, 2008 Page xvii of lx

REJ09B0189-0400

Item

Page

Revisions (See Manual for Details)

12.3.2 Operation in

Asynchronous Mode

Figure 12.8

Sample Serial

Transmission

Flowchart

494

Note added

<End>

[1]

Yes

Initialization

Start transmission

Read TDRE flag in SSR

[2]

Write transmit data to TDR

and clear TDRE flag in SSR to 0

Yes

Read TEND flag in SSR

[3]

Yes

[4]

Clear DR to 0 and

set DDR to 1

Clear TE bit in SCR to 0

TDRE = 1

All data transmitted?

TEND = 1

Break output?

[1] SCI initialization:

The TxD pin is automatically

designated as the transmit data

output pin.

After the TE bit is set to 1, a frame

of 1s is output, and transmission is

enabled.

[2] SCI status check and transmit data

write:

Read SSR and check that the

TDRE flag is set to 1, then write

transmit data to TDR and clear the

TDRE flag to 0.

[3] Serial transmission continuation

procedure:

To continue serial transmission,

read 1 from the TDRE flag to

confirm that writing is possible,

then write data to TDR, and then

clear the TDRE flag to 0. Checking

and clearing of the TDRE flag is

automatic when the DMAC or

DTC* is activated by a transmit

data empty interrupt (TXI) request,

and date is written to TDR.

[4] Break output at the end of serial

transmission:

To output a break in serial

transmission, set DDR for the port

corresponding to the TxD pin to 1,

clear DR to 0, then clear the TE bit

in SCR to 0.

Note: * The TDRE flag check and clear

operations are performed

automatically

by DTC only when the DTC

DISEL bit is 0 and furthermore

the transfer counter is not 0.

Therefore the CPU must clear

the TDRE flag when either

DISEL is 1 or when DISEL is 0

and furthermore the transfer

counter is 0.

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